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Altera_Forum
Honored Contributor I
1,617 Views

TimeQuest found "Unconstrained Paths"

Hello, 

 

Before approach "timing analysis" I've studied the ryan scoville's "TimeQuest User Guide", that can be found here: 

 

http://alterawiki.com/wiki/timequest_user_guide 

 

In the section, related to i/o constraints, a straightforward approach is alaborated. This approach (to my opinion) is based on 2 key-points: 

  1. Applying of the I/O constraints is iterative process and begins with -max 0 and -min 0, (for set_input_delay and set_output_delay) that are adjusted with each iteration 

  2. For set_output_delay it's virtual clock that is used 

 

 

Commenting 2nd point author present a diagram where FPGA drives an external device, that is clocked by an external clock (by the way I found this diagram in others manual as well) 

I'm not sure that such scenario is versatile ... 

For example, on my board "Terasic SoC DE1", the SDRAM (as well as other peripherals) is clocked from FPGA. 

So, apparently, this diagram with external clock isn't relevant for my case, isn't it ? 

So, how .sdc setup should be modified to take into account that clock that drives output device is generated inside FPGA (e.g. by PLL) ? 

It seems that ryan scoville's manual has answer to this question. 

On the page 88 (section dedicated to set_input_delay/set_output_delay) we can read the following: 

 

 

--- Quote Start ---  

-clock - This is the clock driving this external register. In almost all cases this clock should be a virtual clock. The only major exception is for source-synchronous outputs, where the -clock should be the name of a create_generated_clock that is applied to the port driving out the clock. 

--- Quote End ---  

 

 

In my setup I want to constraint interface to sdram, so the "major exception" seems matching my case. 

The "generated clock" I "picked" from TimeQuest Clocks report. 

 

Here below is my .sdc file, that I processed with timequest

And the timequest analysis reports ... that all I/O ports that go to SDRAM are unconstrained !!! 

Where I've been mistaken ? 

Thanks in advance. 

 

create_clock -name clk -period 20 [get_ports clk] 

create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} 

 

 

derive_pll_clocks 

derive_clock_uncertainty 

 

 

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] 

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] 

set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] 

 

 

set clk_ext [get_nets u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk] 

 

 

# Constraint SDRAM DATA for input 

set_input_delay -clock $clk_ext -max 0 [get_ports sdram_dq 

[*]] 

set_input_delay -clock $clk_ext -min 0 [get_ports sdram_dq 

[*]] 

 

 

# Constraint SDRAM DATA for output 

set_output_delay -clock $clk_ext -max 0 [get_ports sdram_dq 

[*]] 

set_output_delay -clock $clk_ext -min 0 [get_ports sdram_dq 

[*]] 

 

 

# Constraint DRAM ADDRESS for output 

set_output_delay -clock $clk_ext -max 0 [get_ports sdram_addr 

[*]] 

set_output_delay -clock $clk_ext -min 0 [get_ports sdram_addr 

[*]] 

 

 

# Constraint SDRAM Controlss for output 

set_output_delay -clock $clk_ext -max 0 [get_ports {sdram_bank 

[*] sdram_dqm 

[*] sdram_cas_n sdram_ras_n sdram_cke sdram_cs_n sdram_we_n}] 

set_output_delay -clock $clk_ext -min 0 [get_ports {sdram_bank 

[*] sdram_dqm 

[*] sdram_cas_n sdram_ras_n sdram_cke sdram_cs_n sdram_we_n}] 

 

 

set_false_path -from [get_ports sw*] 

set_false_path -from [get_ports key*] 

 

 

set_false_path -from * -to [get_ports led*] 

set_false_path -from * -to [get_ports hex*]
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4 Replies
Altera_Forum
Honored Contributor I
383 Views

Hi,  

 

create generated clock for clock output pin which goes to SDRAM chip and constrain output pins to clk_ext 

 

create_generated_clock -name clk_ext -source set_false_path -to  

 

Create virtual clock and constrain input ports to virtual clock clk_ext_virt 

 

create_clock -name clk_ext_virt -period
Altera_Forum
Honored Contributor I
383 Views

 

--- Quote Start ---  

Hi,  

 

create generated clock for clock output pin which goes to SDRAM chip and constrain output pins to clk_ext 

 

create_generated_clock -name clk_ext -source set_false_path -to  

 

Create virtual clock and constrain input ports to virtual clock clk_ext_virt 

 

create_clock -name clk_ext_virt -period  

--- Quote End ---  

 

 

Hi, 

 

Thanks for suggestion ... but "generated clock" is already created by the command derive_pll_clocks

There are 2 such clocks (with same frequency) that output from the PLL. 

One of them clocks all components in Qsys (including CPU NIOS II), whereas other goes out and clocks sdram

The clock that goes to sdram I pick from the timequest clock analysis and put it into .SDC using following instruction: 

 

set clk_ext [get_nets u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk] 

 

Then I use it as clock source in set_input_delay and set_output_delay

 

As I understood (perhaps incorrectly) when the command derive_pll_clocks is used, it fixes all PLL-generated clocks, isn't it ? 

 

Concerning virtual clock, in all documents that I saw before, virtual clock is used only if clock is generated out of FPGA, whereas in my case clock is generated inside FPGA. 

Again, perhaps my perception isn't correct ?
Altera_Forum
Honored Contributor I
383 Views

 

--- Quote Start ---  

but "generated clock" is already created by the command derive_pll_clocks. 

--- Quote End ---  

 

 

with derive_pll_clocks command you have created clocks for PLL output pins. In addition as I suggested you will create clock for clock out pin which drives SDRAM. Your clock tree should look something like this: 

 

PLL input clock| 

-PLL output C0| [/INDENT] 

-PLL output C1|[/INDENT] 

-CLK ext|[/INDENT][/INDENT][/INDENT] 

 

By using CLK ext you will constrain your output relative to actual clock which drives SDRAM.  

 

As for input constrains you are right. You should use same CLK ext clock.
Altera_Forum
Honored Contributor I
383 Views

Finally it works ... in sense that there is no more unconstrained paths. 

Well, TimeQuest reports timing violations, but this is another story. 

Here below - modified .sdc

If I properly understood your last message, you agree that for my case virtual clock is irrelevant ? 

 

create_clock -name clk -period 20 [get_ports clk] 

create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} 

 

derive_pll_clocks 

derive_clock_uncertainty 

 

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] 

set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] 

set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo] 

 

create_generated_clock -name clk_ext_sdram -source [get_pins {u0|pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {sdram_clk}] 

set_false_path -to [get_ports {sdram_clk}] 

 

# Constraint SDRAM DATA for input 

set_input_delay -clock clk_ext_sdram -max 0 [get_ports sdram_dq[*]] 

set_input_delay -clock clk_ext_sdram -min 0 [get_ports sdram_dq[*]] 

 

# Constraint SDRAM DATA for output 

set_output_delay -clock clk_ext_sdram -max 0 [get_ports sdram_dq[*]] 

set_output_delay -clock clk_ext_sdram -min 0 [get_ports sdram_dq[*]] 

 

# Constraint DRAM ADDRESS for output 

set_output_delay -clock clk_ext_sdram -max 0 [get_ports sdram_addr[*]] 

set_output_delay -clock clk_ext_sdram -min 0 [get_ports sdram_addr[*]] 

 

# Constraint SDRAM Controlss for output 

set_output_delay -clock clk_ext_sdram -max 0 [get_ports {sdram_bank[*] sdram_dqm* sdram_cas_n sdram_ras_n sdram_cke sdram_cs_n sdram_we_n}] 

set_output_delay -clock clk_ext_sdram -min 0 [get_ports {sdram_bank[*] sdram_dqm* sdram_cas_n sdram_ras_n sdram_cke sdram_cs_n sdram_we_n}] 

 

set_false_path -from [get_ports sw*] 

set_false_path -from [get_ports key*] 

 

set_false_path -from * -to [get_ports led*] 

set_false_path -from * -to [get_ports hex*]
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