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TimeQuest range values for time values

Altera_Forum
Honored Contributor II
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I've run into an interesting problem while specifying a time value for the create_generated_clock command: 

 

create_generated_clock -name {diag_clk_21} -divide_by 4194304 -source [get_pins inst|the_pll|the_pll|altpll_component|pll|clk[2]] [get_pins inst100|lpm_counter_component|auto_generated|counter_cella21|regout] 

 

These are the errors that I am receiving: 

 

warning: the period, rise edge, or fall edge of clock: diag_clk_21 was found to be outside of the range of acceptable time values. the minimum acceptable time value is -2147483.647 and the maximum acceptable time value is 2147483.647. this clock will be ignored. 

warning: the calculated rise and fall waveform edges for clock: diag_clk_21 were found to be identical (rise: 0.000, fall: 0.000). this clock will be ignored. 

 

Does anyone have an idea of how to increase the range of acceptable values for the -divide_by option?
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Altera_Forum
Honored Contributor II
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With this restriction, your setup requirement is limited to 2,147,483.647. There is no path that could ever not meet timing, so if you reduce the -divide_by to get something in this range, it really doesn't matter. Your positive slack will still be in the millions. 

 

(You might need to worry about hold times, since it looks like you're gating a clock...) 

 

The limitation might be there for a reason(it might be a range that allows the TimeQuest enginge to run faster, or something like that.) You can file an SR to have it increased, but again, you could modify your requirement to fit that range without problems.
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Altera_Forum
Honored Contributor II
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I've noticed that the largest value I can use for the -divide_by option is 32768 (2^15). If I use 65536 (2^16), then I get these warnings: 

 

warning: the period, rise edge, or fall edge of clock: diag_clk_21 was found to be outside of the range of acceptable time values. the minimum acceptable time value is -2147483.647 and the maximum acceptable time value is 2147483.647. this clock will be ignored. 

warning: the calculated rise and fall waveform edges for clock: diag_clk_21 were found to be identical (rise: 0.000, fall: 0.000). this clock will be ignored. 

 

The source clock is 25MHz. This is what I've found, so yes there are limits.
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