Timequest - Constraining input data paths for minimum skew

[Altera_Forum]

In my system I need to detect the first of eight digital inputs to go active. I need to differentiate between inputs that may go active within 1ns of each other. 

 To do this I feed the each of the sets inputs to four d-type registers. Each register has a different 250MHz clock 90 degrees out of phase from the clocks either side of it. I use an internal pll to generate the clocks.   I wish to constrain the design to provide the minimum data path skew between the different paths from the input pins to the data inputs of the registers. Please can anyone give me some hints? Thanks   I have tried using set input delay referenced to a virtual clk_ext but as Quartus puts that in phase with the only one of my pll clocks then it tries to force the data paths clocked from the out of phase clocks to meet the timing constraints of the external virtual clock, not what i want atall   Thanks  Dave

[Altera_Forum]

bump. 

 Would love to hear more on this topic. Generally, constraining skew seems to be a common question.  -A

[Altera_Forum]

Have you tried setting input delay with reference to each of PLL outputs separately? 

 If you know as well your board delay differences you can accommodate that in your delay settings.   Overall I don't see the feasibility of your approach,FPGA timing tools are not good enough at 1ns resolutions...   another unofficial method is this:   if any output is '1', reset all asynchronously. So only first to rise will have a short pulse provided you latch the decision.