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15320 Discussions

Timequest for asynchronous design

VFres
Beginner
282 Views

​Hello,

Is it possible to use timequest to have information about delays inside an asynchronous design?

I would like to know the time between 2 nodes that are not linked by any clock. I have just combinatorial functions.

But if I try to use the report_path command:

report_path -from [x] -to [y]

I just receive:

Report Path: No paths were found

Thanks for help

 

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4 Replies
sstrell
Honored Contributor III
152 Views

You don't mention what x and y are (ports, pins?) but the main command to use is report_timing. It should look something like this:

 

report_timing -setup -from [get_[pins/ports] x] -to [get_[pins/ports] y]

 

#iwork4intel

KhaiChein_Y_Intel
152 Views

Hi,

 

Does the design contain any registers? You can see the delay for a combinational logic between registers by reporting the timing between the registers. The Timing Analyzer recognizes and analyzes the following timing paths only.

  • Edge paths—connections from ports-to-pins, from pins-to-pins, and from pins-to-ports.
  • Clock paths—connections from device ports or internally generated clock pins to the clock pin of a register.
  • Data paths—connections from a port or the data output pin of a sequential element to a port or the data input pin of another sequential element.
  • Asynchronous paths—connections from a port or asynchronous pins of another sequential element such as an asynchronous reset or asynchronous clear.

Thanks.

Best regards,

KhaiY

VFres
Beginner
152 Views

​Hi,

Thank you for your answer.

So if I don't have any register there is no way to know delays between luts?

report_timing gives the same:

"Report Timing: No setup paths were found" 

Best regards

 

 

 

skyjuice
Employee
152 Views

report_path should be able to do what you want. Just make sure you use the correct filter as what sstrell mentioned

Reply