I don;t see -phase 90 option when I create a generated clock through Timequest for PLLs. In PLL IP, I pick 90 degree phase shift. I compiled the design. In fitter resource usage summary, I confirm that PLL has 90 degree phase shift. In Timequest, When I pick derived PLL clocks then write to SDC file, I don;t see generated clock with 90 degree phase shift. Am I missing something?
