Timequest unconstrained paths clock summary

Altera_Forum · ‎02-19-2016

Hello and good morning from Germany.

i have got a problem with the timequest Analyser tool. In the following code you can see my first test of the RS232 Interface. It works but if i start the timequest tool, the timequest tool said: RS232_CONTROL:RS232CNT|RS232_RX:RS232RX|l_mstate.IDLE~1 is a clock. But it isn't a clock. Whats happen? could you please help me?


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RS232_RX is
    generic(    CLK_MUL: natural := 6;
            BITS: natural := 8;
            STOPBIT: natural range 0 to 1 := 0);
    port(        RESET: in bit;
            NDATA: in bit; -- new data
            READY: out bit; -- ready for new data
            BCLK: in bit;
            databit: in bit_vector(BITS-1 downto 0);
            DO: out bit);
end RS232_RX;
architecture STRUCT of RS232_RX is
    type state is (IDLE, START, SEND, STOP);
    signal l_databit: bit_vector(BITS-1 downto 0);
    signal iclk: bit := '0';
    signal l_mstate: state;
    signal l_obit: bit := '1'; --idle bit
    signal l_ready: bit := '0';
begin
P1:     process(BCLK,RESET,databit,NDATA,l_ready) 
    variable v_counter: integer range 0 to CLK_MUL := 0; --integer
    variable v_bcnt: integer range 0 to BITS-1 := 0; --integer rang 0 bis BITS; 
    variable vcnt_stbbit: integer range 0 to 1 := STOPBIT; --anzahl der stopbits
    begin
        if RESET='1' then
            l_mstate <= IDLE; --set the machine to start.
            v_counter := 0; -- reset v_counter
            l_ready <= '1'; --set ready to not ready for new data i am in the process.
        elsif NDATA = '1' and l_ready = '1' then --new data? 
                l_databit <= databit; --nur bei reset zuweisen
                l_mstate <= START;
                l_ready <= '0';
        elsif BCLK'event and BCLK='0' then
            if v_counter=0 then
                v_counter := CLK_MUL-1;
                case l_mstate is
                    when IDLE => null;                        
                        l_mstate <= IDLE; --set the machine to start.
                    when START =>                    
                        l_obit <= '0';
                        l_mstate <= SEND;
                        v_bcnt := BITS-1;
                        vcnt_stbbit := STOPBIT;
                    when SEND =>    
                        l_obit <= l_databit(0);
                        l_databit <= '0' & l_databit(BITS-1 downto 1);
                        if v_bcnt = 0 then
                            l_mstate <= STOP;
                        else
                            v_bcnt := v_bcnt -1;
                        end if;
                    when STOP =>    
                        l_obit <= '1';
                        if vcnt_stbbit = 0 then
                            l_mstate <= IDLE;
                            l_ready <= '1'; --ready for new data
                        else
                            vcnt_stbbit := vcnt_stbbit-1;
                        end if;
                end case;
            else
                v_counter := v_counter - 1;
            end if;
        end if;    
    end process P1;
PO:     process(l_obit,l_ready)
    begin
        READY <= l_ready;
        DO <= l_obit;
    end process PO;
end STRUCT;

Thanks.

PS.: In the attachment is a screen shoot of the timequest analyzer.

Altera_Forum · ‎02-19-2016

This seems a very odd setup. Why are NDATA and l_ready used to asynchronously set the state machine and data bit? thats not very timing safe. They should be part of the logic that flips the design out of the IDLE state. This is the only reason I can think of it's chosen to make the idle state as some form of clock in your async logic.