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New Contributor I
111 Views

Timing Constraints.

Hi sir/madam.

I'm working on MAX10  FPGA to interface USB 2.0 with FPGA to send image data pixels to PC . Problem is my verilog design is not able achieve timing constraints (designed for 60 MHz clock and achieved to 58 MHz ) i saw this in timing analyzer in quartus software. Can i get help on how to design FPGA projects to meet timing constarints. I'm new to FPGA design technology.

Thanks in advance.

  

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8 Replies
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Novice
103 Views

In Quartus you can use the Timing Optimization Advisor from menu:
 Tools/Advisors/Timing Optimization Advisor
to get some good advice.

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New Contributor I
99 Views

Thanks for the reply sir. Also can i get any design tips for fpga design.

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Moderator
88 Views

There's lots of training available for timing analysis.  Start here:

Timing Analyzer: Introduction to Timing Analysis

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New Contributor I
83 Views

Thank you sir.

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80 Views

Hi,


You may also refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbo.... There are some examples on how to constrain a design.


Thanks

Best regards,

Khai Chein


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78 Views

Hi,


You may also refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbo.... There are some examples on how to constrain a design.


Thanks

Best regards,

KhaiY


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Novice
74 Views

This document gives advice on many things concerning timing:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an584.pdf

Also some design tips are listed.

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New Contributor I
42 Views

Thank sir

 

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