Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing analyser not reporting all the I/O paths

Bhavanag
Beginner
221 Views

we could see only 32 paths in the GUI of Timing analyser and we have more I/Os to be reported.

As part of Static Timing Analysis, we are using the command line option “quartus_sta  $PROJECT_NAME --do_report_timing --sdc=

As part of Static Timing Analysis, we are using the command line option “quartus_sta  $PROJECT_NAME --do_report_timing --sdc=<sdc file name> --64bit –multicorner” , even with this command line option, we are not seeing all the I/O paths in the STA report.

 

And we don’t have warnings for the Timing analyser and all the I/O paths are constrained.

 

We have also used the command that you shared, in the Timing analyser GUI and still we could not see all the I/O paths.

 

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2 Replies
Nurina
Employee
191 Views

Hi,


Not sure why this happened. Can you attach your .qar file here? To generate this, go to Project>Archive Project.


Thanks,

Nurina


Nurina
Employee
129 Views

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

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