migrate to Quartus Pro

[dsun01]

Dear Support/Expert

I have a project from Intel which can be compiled by Standard version. Just got a license of the PRO, so try to upgrade to Pro version. 

Here are some dump from the message. 

Info: Started running qsys-validate on Platform Designer system loopback_fifo.qsys
Info: Performing Platform Designer system validation using the command line: c:/intelfpga_pro/21.3/quartus/../qsys/bin/qsys-validate.exe loopback_fifo.qsys
Info: Finished running qsys-validate on Platform Designer system loopback_fifo.qsys
Info: Started running qsys-validate on Platform Designer system ../ip/loopback_fifo.qsys
Info: Performing Platform Designer system validation using the command line: c:/intelfpga_pro/21.3/quartus/../qsys/bin/qsys-validate.exe ../ip/loopback_fifo.qsys
Info: loopback_fifo: All Generic Component instances match their respective ip files.
Info: Finished running qsys-validate on Platform Designer system ../ip/loopback_fifo.qsys
Info: Only synthesis files will be generated.

the tools delete a lot of files here and then show the following message.

Info: Performing IP Generation using the command line: c:/intelfpga_pro/21.3/quartus/sopc_builder/bin/qsys-generate.exe {--family=Arria 10} --part=10AX115H2F34E1SG --block-symbol-file --quartus-project=C:/FPGA/TSW14J57_pro/DDR_XCVR_16lane/prj/jesd204b --rev=jesd204b --top-level-generation=true {--bypass-quartus-project } --clear-output-directory --synthesis=verilog --parallel --batch=../ip/ip/jesd204b/jesd204b_reset_bridge_0.ip --batch=../ip/ip/jesd204b/jesd204b_reg_ctrl_0.ip --batch=../ip/ip/jesd204b/jesd204b_pll_reconfig_0_avmm_translator.ip --batch=../ip/ip/jesd204b/jesd204b_pll_reconfig_0.ip --batch=../ip/ip/jesd204b/jesd204b_pio_1.ip --batch=../ip/ip/jesd204b/jesd204b_onchip_memory2_0.ip --batch=../ip/ip/jesd204b/jesd204b_nios2_reg_ctrl_bram.ip --batch=../ip/ip/jesd204b/jesd204b_nios2_reg_ctrl_0.ip --batch=../ip/ip/jesd204b/jesd204b_mm_master_bfm_0.ip --batch=../ip/ip/jesd204b/jesd204b_mm_clock_crossing_bridge_1.ip --batch=../ip/ip/jesd204b/jesd204b_mm_clock_crossing_bridge_0.ip --batch=../ip/ip/jesd204b/jesd204b_mif_ram.ip --batch=../ip/ip/jesd204b/jesd204b_master_0.ip --batch=../ip/ip/jesd204b/jesd204b_jtag_dbg_master.ip --batch=../ip/ip/jesd204b/jesd204b_jesd_top_qsys_0.ip --batch=../ip/ip/jesd204b/jesd204b_jesd_reset_seq.ip --batch=../ip/ip/jesd204b/jesd204b_jesd_phy_reconfig_avmm.ip --batch=../ip/ip/jesd204b/jesd204b_jesd_device_clk.ip --batch=../ip/ip/jesd204b/jesd204b_fx3_reg_ctrl_avs.ip --batch=../ip/ip/jesd204b/jesd204b_fx3_control_avmm_expt.ip --batch=../ip/ip/jesd204b/jesd204b_export_clk_reset_0.ip --batch=../ip/ip/jesd204b/jesd204b_enc_ddr_mm_bridge_0.ip --batch=../ip/ip/jesd204b/jesd204b_enc_data_gen_0.ip --batch=../ip/ip/jesd204b/jesd204b_emif_0.ip --batch=../ip/ip/jesd204b/jesd204b_dec_ddr_mm_bridge_0.ip --batch=../ip/ip/jesd204b/jesd204b_dec_data_capture_0.ip --batch=../ip/ip/jesd204b/jesd204b_dac_mm_bridge_0.ip --batch=../ip/ip/jesd204b/jesd204b_clkin_50.ip --batch=../ip/ip/jesd204b/jesd204b_clk_iopll_100M.ip --batch=../ip/ip/jesd204b/jesd204b_adc_mm_bridge_0.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_timer.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_pio_status.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_pio_control.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_nios2_mem.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_nios2_gen2_0.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_jtag_uart.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_jtag_dbg_rst_bridge.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_jesd_mm_bridge.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_custom_mm_bridge.ip --batch=../ip/ip/nios2_subsystem/nios2_subsystem_clk_100mhz.ip --batch=../ip/loopback_fifo.qsys --batch=loopback_fifo.qsys --batch=../ip/fx3_iopll.qsys --batch=../ip/fx3_clkctrl.qsys --batch=../ip/fx3_clk_iopll.qsys --batch=../ip/fx3_clk_ctrl.qsys --batch=../ip/ddr_out.qsys --batch=../ip/enc_512b_fifo.qsys --batch=../ip/dec_512b_fifo.qsys --batch=../ip/pclk_pll.qsys --batch=../ip/i2c_sda.qsys --batch=../ip/atx_pll.qsys --batch=../ip/jesd_io_pll.qsys --batch=../ip/jesd204b.qsys --batch=../ip/Jesd204b_mc_rx.qsys --batch=../ip/Jesd204b_mc_tx.qsys --batch=../ip/xcvr_jesd_rx.qsys --batch=../ip/xcvr_jesd_tx.qsys --batch=../ip/xcvr_reset_controller.qsys --batch=../ip/xcvr_rst_rx.qsys --batch=../ip/dec_cap_mem.qsys --batch=../ip/dec_fifo.qsys --batch=../ip/dec_fifo_b.qsys --batch=../ip/enc_data_gen_mem.qsys --batch=../ip/enc_fifo.qsys --batch=../ip/enc_fifo_128to256.qsys --batch=../ip/enc_fifo_b.qsys --batch=../ip/dec_capture_mem.qsys --batch=../ip/ddr2fx3_32bfifo.qsys --batch=../ip/fx32ddr_32bfifo.qsys --batch=../ip/somf_gen_fifo.qsys ../ip/nios2_subsystem.qsys
Info: Batch generation will generate the listed files in this order: C:/FPGA/TSW14J57_pro/DDR_XCVR_16lane/ip/nios2_subsystem.qsys, ../ip/loopback_fifo.qsys, loopback_fifo.qsys, ../ip/fx3_iopll.qsys, ../ip/fx3_clkctrl.qsys, ../ip/fx3_clk_iopll.qsys, ../ip/fx3_clk_ctrl.qsys, ../ip/ddr_out.qsys, ../ip/enc_512b_fifo.qsys, ../ip/dec_512b_fifo.qsys, ../ip/pclk_pll.qsys, ../ip/i2c_sda.qsys, ../ip/atx_pll.qsys, ../ip/jesd_io_pll.qsys, ../ip/jesd204b.qsys, ../ip/Jesd204b_mc_rx.qsys, ../ip/Jesd204b_mc_tx.qsys, ../ip/xcvr_jesd_rx.qsys, ../ip/xcvr_jesd_tx.qsys, ../ip/xcvr_reset_controller.qsys, ../ip/xcvr_rst_rx.qsys, ../ip/dec_cap_mem.qsys, ../ip/dec_fifo.qsys, ../ip/dec_fifo_b.qsys, ../ip/enc_data_gen_mem.qsys, ../ip/enc_fifo.qsys, ../ip/enc_fifo_128to256.qsys, ../ip/enc_fifo_b.qsys, ../ip/dec_capture_mem.qsys, ../ip/ddr2fx3_32bfifo.qsys, ../ip/fx32ddr_32bfifo.qsys, ../ip/somf_gen_fifo.qsys, ../ip/ip/jesd204b/jesd204b_reset_bridge_0.ip, ../ip/ip/jesd204b/jesd204b_reg_ctrl_0.ip, ../ip/ip/jesd204b/jesd204b_pll_reconfig_0_avmm_translator.ip, ../ip/ip/jesd204b/jesd204b_pll_reconfig_0.ip, ../ip/ip/jesd204b/jesd204b_pio_1.ip, ../ip/ip/jesd204b/jesd204b_onchip_memory2_0.ip, ../ip/ip/jesd204b/jesd204b_nios2_reg_ctrl_bram.ip, ../ip/ip/jesd204b/jesd204b_nios2_reg_ctrl_0.ip, ../ip/ip/jesd204b/jesd204b_mm_master_bfm_0.ip, ../ip/ip/jesd204b/jesd204b_mm_clock_crossing_bridge_1.ip, ../ip/ip/jesd204b/jesd204b_mm_clock_crossing_bridge_0.ip, ../ip/ip/jesd204b/jesd204b_mif_ram.ip, ../ip/ip/jesd204b/jesd204b_master_0.ip, ../ip/ip/jesd204b/jesd204b_jtag_dbg_master.ip, ../ip/ip/jesd204b/jesd204b_jesd_top_qsys_0.ip, ../ip/ip/jesd204b/jesd204b_jesd_reset_seq.ip, ../ip/ip/jesd204b/jesd204b_jesd_phy_reconfig_avmm.ip, ../ip/ip/jesd204b/jesd204b_jesd_device_clk.ip, ../ip/ip/jesd204b/jesd204b_fx3_reg_ctrl_avs.ip, ../ip/ip/jesd204b/jesd204b_fx3_control_avmm_expt.ip, ../ip/ip/jesd204b/jesd204b_export_clk_reset_0.ip, ../ip/ip/jesd204b/jesd204b_enc_ddr_mm_bridge_0.ip, ../ip/ip/jesd204b/jesd204b_enc_data_gen_0.ip, ../ip/ip/jesd204b/jesd204b_emif_0.ip, ../ip/ip/jesd204b/jesd204b_dec_ddr_mm_bridge_0.ip, ../ip/ip/jesd204b/jesd204b_dec_data_capture_0.ip, ../ip/ip/jesd204b/jesd204b_dac_mm_bridge_0.ip, ../ip/ip/jesd204b/jesd204b_clkin_50.ip, ../ip/ip/jesd204b/jesd204b_clk_iopll_100M.ip, ../ip/ip/jesd204b/jesd204b_adc_mm_bridge_0.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_timer.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_pio_status.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_pio_control.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_nios2_mem.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_nios2_gen2_0.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_jtag_uart.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_jtag_dbg_rst_bridge.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_jesd_mm_bridge.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_custom_mm_bridge.ip, ../ip/ip/nios2_subsystem/nios2_subsystem_clk_100mhz.ip
Error: Could not find file to batch generate: loopback_fifo.qsys

what this error means? and how to correct it? 

thanks,

David Sun

[SyafieqS]

Hi Sun,

May I know how did you upgrade it? Like you straight away open the std design and compile it in Pro?

[SyafieqS]

Are you targeting same device? if different device, selecting a migration device impacts pin placement because some pins may serve different functions in different device densities or package sizes. If same design of same device from STD, this seem more to IP upgrade, can you try regenerate all the qsys for sanity check in PD.

[SyafieqS]

Hi Sun,

I believe this might be related to migration issue from STD to Pro. I recommend you to look at link below Migrating to the Intel® Quartus® Prime Pro Edition Software. It describes flow how to migrates and what need to be done like project assignment, sdc, script etc. You probably need to regenerate all the IPs in order to open the IP.

https://www.youtube.com/watch?v=P_6gemOLtjE

[dsun01]

thanks for all the replies.  I don't know how and why this happens, the problem is some script or TCL didn't run correctly or something, so the 

Error: Could not find file to batch generate: loopback_fifo.qsys, there are two links to the same file. one is in the correct directory, one is point to project directory, I just duplicate one copy to the project directory, then it compiled. 

thank you again for all the replies, we can mark this thread as solved. 

to answer some of the above question. the device upgraded first with an standard version which compiled, thank I open the standard 18.1 version to PRO 21.3. now it compiles. I will ask another question in the timing analysis thread. hope someone can help me.