Timing constraints for Nios peripherals

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Timing constraints for Nios peripherals

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Hi,

I currently work on a design containing a Nios II processor and a LAN91C111 ethernet peripheral.

The peripheral communicates with the FPGA-external controller through an asynchronous interface, controlled by read and write strobes. How do I contrain timing for such an interface? I understand I have to define the strobes as clocks and then set multicycles, but how can I do that when I don't know anything about the peripheral implementation?

Best regards,

loevinnen

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