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JPrig
Beginner
211 Views

Timing constraints when the clock is recovered from data

Hi,

I have a serial data stream which arrives at a CPLD pin. This data stream feeds a clock recovery entity which contains a PLL with dynamic phase reconfiguration. The output of the clock recovery entity is a clock which is always edge aligned in the middle of the data bit window. This clock is then used to sample the input data at a register. I attempted to illustrate the concept in the attached screenshot.

 

I assume I need to constrain the maximum skew between the pin-register path and pin-clock recovery logic path, since the skew will eat up the setup and hold margins at the register. I think I also need to constrain the timing at the register input. I am however unsure how...

 

I tried to set input delays relative to clk_resync directly, since I know that I always have around half of a clock period in setup and hold. But the Timing Analyzer then complains on the path from the pin to the clock recovery logic, because it thinks that the data at the pin is lauched by clk_resync, which I think is not correct. Please advise .

 

Regards, Julia

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3 Replies
19 Views

Hi,

 

Can you share the sdc and the Timing Analyzer reports?

 

Thanks

JPrig
Beginner
19 Views

Hi,

here are the files you asked for. I changed the constraints since my original post, but I am still not sure if they are correct.

The part for the re-synchronization circuit start at line:

# Amplifier transmit clock (line 78)

 

I now define a virtual clock which starts 180 degrees out of phase. I constrain the input data pin AMP_TXD to this clock with a 1 ns margin. This is just a number I assumed to cover for re-synchronization accuracy.

Then I set a false path from this virtual clock to a high frequency sampling clock inside the re-synchronizer. This high frequency clock has the same phase as clk_resync, but 4 times the frequency and is used to sample input data and look for edges.

 

The timing analyzer does not report any errors for this version.

 

Regards,

Julia

19 Views

Hi,

 

If you set false_path assignment to the clock, you will not see the violation in the timing report. If you set false path to the virtual clock and the high frequency sampling clock, the path will not be analyzed and we cannot make sure that the data is sampled correctly.

 

Thanks.

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