Why do I use FPGA to compile a program with different results?

[FWang44]

Or if the A signal is perfect, I move another B signal that is not relevant. After compiling, A is useless. Timing is correct. . Please ask the relevant personnel to guide me. Many people around me have such problems.Or if the A signal is perfect, I move another B signal that is not relevant. After compiling, A is useless. Timing is correct. . Please ask the relevant personnel to guide me. Many people around me have such problems.

[sstrell]

Without seeing a design or code to try, there is no way to answer your question. There are many factors that affect how a design gets compiled or recompiled. Can you provide an example of what you're talking about?

#iwork4intel

[KhaiChein_Y_Intel]

Hi,

May I know if you have any updates? Can you provide the example?

Thanks.