Timing issue for divison

[Altera_Forum]

Hello there, 

 I have the following HDL code, which mainly deals with divison.   assign mod_lo_div2 = (mod_lo_div == 32'b0) ? 100 : mod_lo_div; assign t_pump_low0 = clk_divd_p1 - capped_duty_cycle; assign t_pump_diff = t_pump_low0_reg / mod_lo_div_reg;     always @(negedge resetn or posedge clk) begin if(~resetn) begin mod_lo_div_reg <= 100; t_pump_low0_reg <= 0; t_pump_low1_reg <= 0; mul_cyc_cnt <= 0; end else begin if(mul_cyc_cnt < 4) mul_cyc_cnt <= mul_cyc_cnt + 1; else mul_cyc_cnt <= 0;   if(mul_cyc_cnt == 4) begin mod_lo_div_reg <= mod_lo_div2; t_pump_low0_reg <= t_pump_low0; t_pump_low1_reg <= t_pump_low0_reg - t_pump_diff; end else begin mod_lo_div_reg <= mod_lo_div_reg; t_pump_low0_reg <= t_pump_low0_reg; t_pump_low1_reg <= t_pump_low1_reg;  end end end   The constraints for the above in a SDC file  set_multicycle_path -from [get_clocks {inst|the_cpu_pll|sd1|pll7|clk[2]}] -to [get_pins {inst|the_z_pwm_0|z_pwm_0|task_logic|t_pump_low1_reg*|data*}] -setup -end 4 set_multicycle_path -from [get_clocks {inst|the_cpu_pll|sd1|pll7|clk[2]}] -to [get_pins {inst|the_z_pwm_0|z_pwm_0|task_logic|t_pump_low1_reg*|data*}] -hold -end 1     The timing requirements are not met as shown in an attached file.   Please have a look and give some clue.   Many thanks.

[Altera_Forum]

Retry after removing the final else statement: 

 else begin  mod_lo_div_reg <= mod_lo_div_reg;  t_pump_low0_reg <= t_pump_low0_reg;  t_pump_low1_reg <= t_pump_low1_reg;  end

[Altera_Forum]

Thank you very much indeed. Retry after removing the final else statement, timing requirements are not met. The timing results are attached where the names of some variables are changed from "*low*" to "*lo*".

[Altera_Forum]

Do you have sufficient pipelining in your lpm_divider? Maybe it would help if you increase the pipeline stages of the divider?

[Altera_Forum]

Since it's a cascade of subtractions it will be very slow without pipelining. I recommend taking a look at the lpm_div megafunction and factoring the pipelining into your surrounding logic instead. If I remember correctly a 32-bit division on Cyclone II -6 with only two pipeline stages was around 16MHz.

[Altera_Forum]

Please give tell me how to increase the pipeline stages of the divider? Your further suggestions are highly appreciated.

[Altera_Forum]

Hi BadOmen, 

 Please give me more hints on how to. Your kind help is highly appreciated.

[Altera_Forum]

You can easily adjust it from the megawizard.

[Altera_Forum]

Instantiate lpm_divide instead of typing '/' into your HDL and set the latency accordingly (see fpgabuilder's post with a screenshot of the latency setting).