Timing simulation looks same as functional simulation in Quartus Introduction tutorial

[CZHE0]

I'm trying to follow the Quartus Introduction tutorial from https://fpgauniversity.intel.com/redirect/materials?id=/pub/Intel_Material/14.1/Tutorials/Verilog/Quartus_II_Introduction.pdf. This is just a simple XOR.

However, at the step where I run timing simulation, I do not see any delay in the waveform as the tutorial shows. Instead, it looks identical to what I see in functional simulation.

What am I missing? I'm using Quartus Prime Lite edition 18.1.0 Build 625. I've configured Assignments -> Settings -> Simulation to use Modelsim-Altera. I also noticed that after compilation, 'Timing Analyzer' is red and warns about unconstrained paths, so perhaps I'm missing something here?

[Kenny_Tan]

May I know what device that you were using? We no longer encourage customer to use timing simulation as it is slow. We encourage customer to use timing analyzer and write the constrain for it.

[CZHE0]

Hi KTan9, I'm using the Cyclone V GX Starter Kit. Is it supported?

Also, is there a tutorial I could refer to for 'use timing analyzer and write the constrain for it'?

[Kenny_Tan]

nope. V series is not support timing simulation. You can refer to https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html for the tutorial. make sure you attend all the prerequisite and the following module