Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Timing violations from Synopsys Synphony to Quartus

Altera_Forum
Honored Contributor II
1,141 Views

Hello, 

 

did anyone have problems in meeting timing constraints in Quartus after that Synphony (Simulink library to generate VHDL code) reported all timing constraints where met? 

 

Please find in this previous post of mine more details: 

 

http://www.alteraforum.com/forum/showthread.php?p=138836#post138836 

 

Thanks
0 Kudos
0 Replies
Reply