Total Registers Used = 0

[Altera_Forum]

Dear all, 

I have a strange problem with synthesising my design. the problem is when I have a top level that connects my board signals to my design logic I get every thing synthesised away.  I'm using Verilog-2001 HDL My design hierarchy is as follow:  

• Board Top Level 
• My Design To Level Instance 
• My design Modules Instances 

   When I synthesise my design as top level every thing is synthesised just fine, but when I add one more level on top of that I got nothing, every thing is synthesised away !!  Please give me a clarification to this strange problem.  Thank you.

[Altera_Forum]

This happens, if either no top entity outputs are connected to the design, or the outputs are all constant, e.g. because you didn't connect clock or reset inputs.

[Altera_Forum]

Of course I did connected my DE2_70 CLOCK_50 into my design. Also, I connected KEY[0] as a reset signal. However, I'm still having the problem

[Altera_Forum]

--- Quote Start ---  Of course I did connected my DE2_70 CLOCK_50 into my design. Also, I connected KEY[0] as a reset signal.   --- Quote End ---   O.K., but something is obviously missing, Quartus is following an exact method to determine which parts of the design can be removed.

[Altera_Forum]

Yep you were right, I was not having any output to the board. Once I added a dummy output every thing got synthesized jut fine. 

Thank you for your clearification.