Type do not match for port

[Altera_Forum]

--- Quote Start ---  WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Types do not match for port x_in WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error. WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Types do not match for port u_in WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error. WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Types do not match for port err WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error. WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Types do not match for port yn WARNING[1]: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error.  --- Quote End ---    LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity PhamNT is port(x_in,kd,ki,kp :in signed(15 downto 0):=(others => '0'); clk :in std_logic:='0'; clk_op :in std_logic:='0'; yn :out signed (15 downto 0):=(others => '0') ); end PhamNT; ARCHITECTURE structural OF PhamNT IS signal u,y :signed(15 downto 0):=(others => '0'); --x(n-1),Y(n-1) signal err :signed(15 downto 0):=(others => '0'); signal go :std_logic:='0'; signal pl_go :std_logic:='0'; signal start : std_logic:='0'; signal mic_in : signed(15 downto 0):=(others => '0'); signal z_out : signed(15 downto 0):=(others => '0'); signal done : std_logic:='0'; signal u_in : signed(15 downto 0):=(others => '0'); component simp_cpu IS PORT(start : in std_logic; mic_in,kd,ki,kp :in signed(15 downto 0); z_out :out signed(15 downto 0); done :out std_logic; clk :in std_logic ); END component; component dtdk_plant is port(x_in :in signed(15 downto 0); u_in :in signed(15 downto 0); go :in std_logic; clk :in std_logic; clk_op :in std_logic; err :out signed(15 downto 0); yn :out signed(15 downto 0); pl_go :out std_logic); end component; begin U_Simp_CPU: simp_cpu port map ( start => pl_go, mic_in => err, kd => kd, ki => ki, kp => kp, z_out => u, done => go, clk => clk_op ); U_dtdk_plant: dtdk_plant port map( x_in => x_in, u_in => u, go => go, clk => clk, clk_op => clk_op, err => err, yn => yn, pl_go => pl_go ); end structural ; When I compile it's ok. But I simulate it error. I did not know this error. Could you help me? Thanks (I use Modelsim)

[Altera_Forum]

May be caused by including ieee.std_logic_unsigned.

[Altera_Forum]

--- Quote Start ---  May be caused by including ieee.std_logic_unsigned.  --- Quote End ---    When I compiled and simulated by Quartus it was ok. The result was nice. But I can not simulate it by Modelsim (Compile by modelsim it was still ok).

[Altera_Forum]

The other explanation is, that the component uses different port types. you didn't show it.

[Altera_Forum]

This is my new program. It's still error with yn and err 

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_signed.ALL; --Use ieee.numeric_std.all; entity PhamNT is port(x_in,kd,ki,kp :in std_logic_vector(15 downto 0):=(others => '0'); clk :in std_logic:='0'; clk_op :in std_logic:='0'; yn :out std_logic_vector (15 downto 0):=(others => '0') ); end PhamNT; ARCHITECTURE structural OF PhamNT IS signal u,y :std_logic_vector(15 downto 0):=(others => '0'); --x(n-1),Y(n-1) signal err :std_logic_vector(15 downto 0):=(others => '0'); signal go :std_logic:='0'; signal pl_go :std_logic:='0'; signal start : std_logic:='0'; signal mic_in : std_logic_vector(15 downto 0):=(others => '0'); signal z_out : std_logic_vector(15 downto 0):=(others => '0'); signal done : std_logic:='0'; signal u_in : std_logic_vector(15 downto 0):=(others => '0'); component simp_cpu IS PORT(start : in std_logic; mic_in,kd,ki,kp :in std_logic_vector(15 downto 0); z_out :out std_logic_vector(15 downto 0); done :out std_logic; clk :in std_logic ); END component; component dtdk_plant is port(x_in :in std_logic_vector(15 downto 0); u_in :in std_logic_vector(15 downto 0); go :in std_logic; clk :in std_logic; clk_op :in std_logic; err :out std_logic_vector(15 downto 0); yn :out std_logic_vector(15 downto 0); pl_go :out std_logic); end component; begin U_Simp_CPU: simp_cpu port map ( start => pl_go, mic_in => err, kd => kd, ki => ki, kp => kp, z_out => u, done => go, clk => clk_op ); U_dtdk_plant: dtdk_plant port map( x_in => y,--x_in, u_in => u, go => go, clk => clk, clk_op => clk_op, err => err, yn => yn, pl_go => pl_go ); end structural ;  this is dtdk_plant component LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_signed.ALL; --Use ieee.numeric_std.all; library lpm; use lpm.lpm_components.all; --use ieee.numeric_std.all; entity dtdk_plant is port(x_in :in std_logic_vector(15 downto 0):=(others => '0'); u_in :in std_logic_vector(15 downto 0):=(others => '0'); go :in std_logic:='0'; clk :in std_logic:='0'; clk_op :in std_logic:='0'; err :buffer std_logic_vector(15 downto 0);--:=(others => '0'); yn :buffer std_logic_vector(15 downto 0);--:=(others => '0'); pl_go :out std_logic:='0' ); end dtdk_plant; ARCHITECTURE structural OF dtdk_plant IS signal u_ant :std_logic_vector(15 downto 0):=(others => '0'); SIGNAL mula1,mulb1 :std_logic_vector(15 downto 0):=(others => '0'); SIGNAL mulr1 :std_logic_vector(31 downto 0):=(others => '0'); SIGNAL adda1,addb1,addr1 :std_logic_vector(15 downto 0):=(others => '0'); constant fi :std_logic_vector(15 downto 0) := "0110011001100110"; constant teta :std_logic_vector(15 downto 0) := "0100000000000000"; signal cnt :std_logic_vector(11 downto 0):=(others => '0'); signal aux :std_logic_vector(15 downto 0):=(others => '0'); begin mull: lpm_mult generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32, LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1) port map(dataa=> mula1,datab=> mulb1,clock=> clk,result=> mulr1); adder1: lpm_add_sub generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1) port map(dataa=>adda1,datab=>addb1,clock=> clk,result=>addr1); GEN:block begin process (clk_op,go) begin if (clk_op'event and clk_op = '1') then if go <= '0' then cnt <= cnt+1; else cnt<=X"000"; end if; if cnt=X"000" then mula1 <= (u_ant); mulb1 <= (teta); elsif cnt=X"001" then adda1 <=mulr1(30 downto 15); elsif cnt=X"002" then mula1 <=(yn); mulb1 <=(fi); elsif cnt=X"003" then addb1 <= mulr1(30 downto 15); elsif cnt=X"004" then aux <= (addr1); u_ant <= (u_in); elsif cnt=X"005" then adda1 <= (x_in); addb1 <= (-aux); elsif cnt=X"006" then err <= (addr1); yn <= (aux); pl_go<='1'; elsif cnt=X"007" then pl_go<='0'; if go='0' then cnt <= X"008"; else cnt<=X"000"; end if; end if; end if; end process; end block gen; end structural;

[Altera_Forum]

I want to say a big thanks for FvM. You are expert in VHDL. 

Those are my errors WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Incompatible modes for port err WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error. WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Incompatible modes for port yn WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error.

[Altera_Forum]

At first sight, the buffer type has been changed to out in the component prototype. Not allowed with older VHDL standards.

[Altera_Forum]

thanks. I's true

[Altera_Forum]

Dear FvM 

Sometime I run my project by ModelSim, some component are not bound. When it runs in Quartus, it's still ok. I don't understand this error. Do you know this error? Thanks This is warning in modelsim.   --- Quote Start ---  # Loading work.tb_cpu(structural) # ** Warning: (vsim-3473) Component 'lop1_a' is not bound. # Time: 0 ns Iteration: 0 Region: /tb_cpu File: D:/Quartus/January_2011/Final 1/Test_bench.vhd # ** Warning: (vsim-3473) Component 'u_simp_cpu' is not bound. # Time: 0 ns Iteration: 0 Region: /tb_cpu File: D:/Quartus/January_2011/Final 1/Test_bench.vhd  --- Quote End ---  

[Altera_Forum]

Could you help me? My project is totally stop :cry: 

When I use this conversation: A := RF(CONV_INTEGER(fld_a)); If fld_a = 0, my result always is "X".  I've already sign the initial value for A is '0' but it still is "X" VARIABLE A :std_logic_vector(15 DOWNTO 0):=(others => '0'); I spent a lot of time for it but I still can not soft. Could you help me? Thank you very much.

[Altera_Forum]

This problem I met when i worked with Modelsim. It still work well with Quartus

[Altera_Forum]

--- Quote Start ---  Component 'lop1_a' is not bound  --- Quote End ---   Usually, you forgot to compile the source containing the component definition.   --- Quote Start ---  A := RF(CONV_INTEGER(fld_a)); If fld_a = 0, my result always is "X".  --- Quote End ---   What is RF()? A function or an array?

[Altera_Forum]

RF is a register file. 

I used fld_a as an address to read the value of RF.  TYPE reg_fileT IS ARRAY(0 TO 8) OF std_logic_vector(15 DOWNTO 0); SIGNAL RF :reg_fileT;

[Altera_Forum]

Then the X most likely means, that a 'X' has been written to the register. You can visualize the register content in Modelsim, and you also can force the register manually to check, if the result changes.

[Altera_Forum]

Oh. Thank you very much. I make a mistake with RF. 

by the way, Can you help me to initial for this RF. TYPE reg_fileT IS ARRAY(0 TO 8) OF SIGNED(15 DOWNTO 0):=(others=>'0');  I can not initial by this way, it had an error. Thank you very much.

[Altera_Forum]

Yes, it must be 2-D. 

TYPE reg_fileT IS ARRAY(0 TO 8) OF SIGNED(15 DOWNTO 0):=(others=>(others=>'0'));

[Altera_Forum]

I'm sorry. Could you check this for me? the quartus still show an error in this declaration. 

Error (10500): VHDL syntax error at data_subsys.vhd(21) near text ":="; expecting ";" Thank you very much.

[Altera_Forum]

You cannot initialise a type, you have to initialise a constant/signal/variable. 

 so do this instead:   TYPE reg_fileT IS ARRAY(0 TO 8) OF SIGNED(15 DOWNTO 0); signal RF : reg_fileT :=(others=>(others=>'0'));

[Altera_Forum]

I got it. You are very kind. Thank you very much.

[Altera_Forum]

I have once more question: 

I program this code and I've already initial all value but the output zzero, ccy, sometime their value are "U", "1", "0". Their value are "1" and "0" it's Ok but the value is "U", I can not soft it. Could you help me?  VARIABLE A,B,C :std_logic_vector(15 DOWNTO 0):=(others => '0'); VARIABLE alu_out :std_logic_vector(15 DOWNTO 0):=(others => '0'); VARIABLE zzero,nneg,ccy :STD_LOGIC:='0'; constant z :std_logic_vector(15 downto 0) := (others => '0');    procedure alu (zzero,nneg,ccy :out STD_LOGIC; alu_out :out std_logic_vector(15 DOWNTO 0); a,b :in std_logic_vector(15 DOWNTO 0):=(others => '0'); alu_op :in UNSIGNED(2 DOWNTO 0):=(others =>'0')) is variable alu_out_reg :std_logic_vector(16 DOWNTO 0):=(others => '0'); variable alu_out_or :std_logic_vector(31 downto 0):=(others => '0'); begin case alu_op is when "000" => alu_out_reg := ("0" & a) + ("0" & b); ------add alu_out := alu_out_reg(15 downto 0); ccy := alu_out_reg(16); if alu_out_reg(15 downto 0) = z then zzero := '1'; else zzero:= '0'; end if; when others => null; end case; end alu;   BEGIN A := RF(conv_integer(fld_a)); B := RF(conv_integer(fld_b)); if control_con = '0' then alu(zzero,nneg,ccy,alu_out,A,B,alu_op); zero <= zzero; neg <= nneg; cy <= ccy; end if; the value of "neg" alway is "U" Thank you very much

[Altera_Forum]

You've set nneg as the output of the procedure, but it's no set to anything inside the procedure, so it will always return 'U'. nneg outside the procedure is completly separate from the nneg inside "alu", so the fact you initialised it doesnt matter, it will always be 'U'. 

 To solve it, either remove nneg as an output from alu, or dont connect the external nneg to alu.