Typical timing analysis cyclone V (on top of existing slow/fast)?

[AEsqu]

Hello,

The setup timing results between slow and fast corners for the Cyclone V is huge.

On a 45 MHz clock domain,

on fast (100C) I get +5.5 ns worst slack

while on slow (100C) I get -5 ns worst slack.

Would it be possible to add the timing model for Typical FPGA sample at 100C too in the timing analyzer of Quartus standard?

Kind Regards,

Alex.

[sstrell]

Can you show your timing reports?  That's strange.

But no, you can only use the models at the extremes.

[AEsqu]

Here the 2 histograms on 2 corners. (same quartus p&r).

[AEsqu]

I took the worst path in slow corner then reporting the timing on the same path but on fast corner,

to compare them.

I can see that the slow corner has double interconnect delay compare to fast corner.

[sstrell]

Fast at 100C is not really the report you should be looking at.  What does your Fast -40C report look like?

[AEsqu]

Temperature does not change much the timings results on the Cyclone V.

See histogram at -40C.

I was wondering if the IC (interconnect) is made out of wire + muxes or buffers that could explain why the values are doubled in slow vs fast.

Could a specialist at Intel react on that?

How would the typical values be, somewhere in between the fast and slow corner or ?  

[sstrell]

Histogram reports aren't super useful here.  Show the detailed slack path report (similar to what you posted 3 posts up) for the same path in the slow 100C and fast -40C corners.  That way you can directly compare the results between different binned devices operating at the extremes of temperatures.

[RichardTanSY_Intel · Accepted solution]

Generally speaking, the slow timing model (what’s the slowest my design will run on the slowest device that met the speed grade, at the lowest voltage in spec and the highest temperature in spec) and the fast timing model(what’s the fastest my design will run on the fastest device, highest voltage and lowest temperature).

Ultimately, to ensure the reliability of your design, it is necessary to meet timing for all four timing corners.

The topic of timing models is quite complex, and I believe the best explanation can be found in the following document:

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01139-timing-model.pdf

Hopefully that answer your inquiries.

Please let me know if you have any further questions or concerns.

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[AEsqu]

Thank You Richard, the doc confirms that there is no typical case analysis and it is englobed in "everything in between fast and slow corners".

Some useful info in the doc as well answering some of my questions (like the low/high user voltage taken into account for slow/fast).

I will do a test with a speed grade +1 faster (speed 6)  to see the impact on the slow analysis,

Edit: I cannot, there is only one speed grade for industrial: Industrial grade devices are offered in the –I7 speed grade.

https://www.intel.com/content/www/us/en/docs/programmable/683801/current/cyclone-v-device-datasheet.html

For example, the routing interconnect delays cannot
be modeled with a simple static value or even a table of
values because there are too many independent electrical
parameters leading to too many configurations. The
capacitive loading, its distribution along the wire, the listening
position, the varying RC as the wire goes through several
metal layers, and the input waveform supplied to any of the
interconnect wires are all determined by the place and route
engine, leading to a wide range of electrical configurations.

Uncetainties:
• Manufacturing process on-die variation
• Rise and fall skew in uncorrelated N- and P-channel
transistor speed
• Clock uncertainty and jitter
• Non-uniform voltage on the power distribution network
(PDN)
• End-of-life degradation effects
• Slight variations in hardware design of equivalent blocks
• Crosstalk

The third aspect of the operating conditions is the relative
speed of each FPGA versus the limit of the speed grade with
which it is marked. This is one aspect that the designer has
no control over. It should also be noted that devices within
one speed grade can still differ slightly in performance,
predominantly due to variation in the manufacturing process.
All devices, however, are guaranteed to be faster than the
limit of the speed grade.

Also, between fast (high voltage) and slow (low voltage), the user voltage supply level are taken into account.

[RichardTanSY_Intel]

Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed.

Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Thank you and have a great day!

Best Regards,

Richard Tan