UART VDHL code not working getting only garbage values

[Altera_Forum]

 0down votefavorite (http://stackoverflow.com/questions/42851856/uart-vdhl-code-not-working-getting-only-garbage-values#)   I am trying to do the code in this link https://www.youtube.com/watch?v=fmmcspgotj4 but i got only garbage values i have posted the code below.the buad rate has set to 9600 using 50 MHz clock by making a counter that counts to 5208 (50MHz/5208 = 9600). I am using a DE0 nano SOC FPGA Altera board. top level uart.vhd          down votefavorite (http://stackoverflow.com/questions/42851856/uart-vdhl-code-not-working-getting-only-garbage-values#)   I am trying to do the code in this link https://www.youtube.com/watch?v=fmmcspgotj4 but i got only garbage values i have posted the code below.the baud rate has set to 9600 using 50 MHz clock by making a counter that counts to 5208 (50MHz/5208 = 9600). I am using a DE0 nano SOC FPGA Altera board. top level uart.vhd   library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;ENTITY UART ISPORT(CLOCK_50: IN STD_LOGIC;SW: IN STD_LOGIC_VECTOR (9 downto 0);KEY: IN STD_LOGIC_VECTOR(3 downto 0);LEDR: OUT STD_LOGIC_VECTOR (9 downto 0);LED: OUT STD_LOGIC_VECTOR (7 downto 0);UART_TXD: OUT STD_LOGIC;UART_RXD: IN STD_LOGIC--GPIO_1: OUT STD_LOGIC_VECTOR (3 DOWNTO 1));END UART;ARCHITECTURE MAIN OF UART ISSIGNAL TX_DATA: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL TX_START: STD_LOGIC:='0';SIGNAL TX_BUSY: STD_LOGIC;--SIGNAL UART_TXD: STD_LOGIC;COMPONENT TXPORT(CLK: IN STD_LOGIC;START: IN STD_LOGIC;BUSY: OUT STD_LOGIC;DATA: IN STD_LOGIC_VECTOR (7 downto 0);TX_LINE: OUT STD_LOGIC);END COMPONENT TX;BEGIN C1: TX PORT MAP (CLOCK_50,TX_START,TX_BUSY,TX_DATA,UART_TXD);PROCESS (CLOCK_50)BEGINIF(CLOCK_50'EVENT AND CLOCK_50 = '1') THENIF(KEY(0)='0' AND TX_BUSY = '0') THENTX_DATA <= SW (7 DOWNTO 0);TX_START <= '1';LED <=TX_DATA;ELSETX_START <= '0';END IF;END IF;END PROCESS;END MAIN;        tx component   library ieee;  use ieee.std_logic_1164.all;use ieee.numeric_std.all;ENTITY TX ISPORT(CLK: IN STD_LOGIC;START: IN STD_LOGIC;BUSY: OUT STD_LOGIC;DATA: IN STD_LOGIC_VECTOR (7 downto 0);TX_LINE: OUT STD_LOGIC);END TX;ARCHITECTURE MAIN OF TX ISSIGNAL PRSCL: INTEGER RANGE 0 TO 5208:=0;SIGNAL INDEX: INTEGER RANGE 0 TO 9 :=0;SIGNAL DATAFLL: STD_LOGIC_VECTOR(9 DOWNTO 0);SIGNAL TX_FLG: STD_LOGIC:= '0';BEGINPROCESS(CLK)BEGINIF (CLK'EVENT AND CLK = '1') THENIF (TX_FLG='0' AND START = '1')THENTX_FLG <= '1';BUSY<='1';DATAFLL(0) <= '0';DATAFLL(9) <= '1';DATAFLL(8 DOWNTO 1) <= DATA;END IF;IF(TX_FLG = '1') THEN IF(PRSCL<5208)THENPRSCL<= PRSCL+1;ELSEPRSCL<= 0;END IF;IF(PRSCL = 2607) THENTX_LINE<= DATAFLL(INDEX);IF(INDEX<9) THENINDEX<= INDEX+1;ELSETX_FLG <='0';BUSY <= '0';INDEX <= 0;END IF; END IF; END IF; END IF;END PROCESS;END MAIN;

[Altera_Forum]

Just took a cursory look, but there are many problems with the code. What is TX_LINE before the start bit? It should be '1' or the receiver won't see the start bit and it should be back at 1 at the end. And why is it changing the bit value in the middle of the bit period? The value of TX_LINE is undefined for the first half of the first bit and you don't get the last half of the stop bit.  

 The TX part of a UART is pretty simple. You would be better off throwing out this code and thinking it through for yourself. Normally, things like counters would be in a separate process and also people would use a FSM and drive outputs based on a current state. For example, TX_FLG is useless.