Uart

[Altera_Forum]

Hi. i have one design that is UART written in verilog code. The simulation is successfully done. However, when i program my design to the DE2 board and connect it to the PC using the RS232, there is no output shown in hyper terminal. i would like to ask a favor that help me to have a look on my coding to check that whether my design got any problem. Your effort would be much appreciated. thanks

[Altera_Forum]

You should show either a ModelSim testbench or a Quartus project with a simulation waveform, to make your statement about successful simulation understandable. Also, without knowing the DE2 project, how can we see, that there should be any output to the RS232 interface at all?

[Altera_Forum]

My project is to test the digital circuit(hardware verification). I have attached a picture of overview of this project and UART_comm simulation waveform. In the waveform, the data_in is the data going the be shifted out.  

  If there is any info wanted, just let me know. Thanks for ur reply.

[Altera_Forum]

Just to add in, the led is on(serial_out) all the time when i assign the serial_out to the led. Before i program, there is voltage across the receive pin. However, when i assign it to transmit pin and program it, there is no voltage across the transmit and receive pin.  

 For your info, the serial_out is active low.

[Altera_Forum]

hello jasonkee111, 

 I have played around with your code and have now a working solution. Configure your hyperterminal as follows:  Baudrate/s: 9600 Databits: 8 Parity: none Stopbits: 1 Flow-Control: none  It is not working perfect, means it now continously sends the last char wich you put into TXD_DATA.  regards, Alex

[Altera_Forum]

Hi there, can someone help me, I plan to used UART to transfer data from DE2-70 read from SRAM to PC trough hyperterminal. The data is 8bit only. Currently I just found the Verilog HDL code for transmitter as per attached. Can anyone help me how to setup this thing?

[Altera_Forum]

@ spellic (http://www.alteraforum.com/forum/member.php?u=11333) 

 Hi could you please explain why division numbers are different for TX and RX in clk_generator module as both of thm are working on same baud rate?

[Altera_Forum]

Rx performs has to perform oversampling of the data stream, so it needs a higher clock rate.

[Altera_Forum]

module Baud_Counter ( 

// Inputs input clk, input reset,   input reset_counters,   // Outputs output reg baud_clock_rising_edge, output reg baud_clock_falling_edge, output reg all_bits_transmitted );  parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_COUNT = 5; parameter BAUD_TICK_COUNT = BAUD_COUNT - 1; //9'd433; parameter HALF_BAUD_TICK_COUNT = BAUD_COUNT / 2; //9'd216;  parameter DATA_WIDTH = 9; parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;  reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter; reg [3:0] bit_counter;  // control baud_counter always @(posedge clk) begin  if (reset == 1'b1)  baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};  else if (reset_counters)  baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};  else if (baud_counter == BAUD_TICK_COUNT)  baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};  else  baud_counter <= baud_counter + 1'b1; end  // control baud_clock_rising_edge signal always @(posedge clk) begin  if (reset == 1'b1)  baud_clock_rising_edge <= 1'b0;  else if (baud_counter == BAUD_TICK_COUNT)  baud_clock_rising_edge <= 1'b1;  else  baud_clock_rising_edge <= 1'b0; end  // control baud_clock_falling_edge signal always @(posedge clk) begin  if (reset == 1'b1)  baud_clock_falling_edge <= 1'b0;  else if (baud_counter == HALF_BAUD_TICK_COUNT)  baud_clock_falling_edge <= 1'b1;  else  baud_clock_falling_edge <= 1'b0; end  // control bit counter always @(posedge clk) begin  if (reset == 1'b1)  bit_counter <= 4'h0;  else if (reset_counters)  bit_counter <= 4'h0;  else if (bit_counter == TOTAL_DATA_WIDTH)  bit_counter <= 4'h0;  else if (baud_counter == BAUD_TICK_COUNT)  bit_counter <= bit_counter + 4'h1; end  // control all_bits_transmitted signal always @(posedge clk) begin  if (reset == 1'b1)  all_bits_transmitted <= 1'b0;  else if (bit_counter == TOTAL_DATA_WIDTH)  all_bits_transmitted <= 1'b1;  else  all_bits_transmitted <= 1'b0; end  endmodule   module RS232_In ( // Inputs input clk, input reset, input serial_data_in, input receive_data_en, // Outputs output reg [(DATA_WIDTH-1):0] received_data, output reg receiving_data, output reg data_received, output baud_clock );  parameter BAUD_COUNT = 9'd434; parameter DATA_WIDTH = 8; parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;  wire shift_data_reg_en; wire all_bits_received;   assign baud_clock = shift_data_reg_en; reg [(TOTAL_DATA_WIDTH - 1):0] data_in_shift_reg; //reg receiving_data; reg prev_receiving_data;    always @(posedge clk) begin  if (reset == 1'b1)  receiving_data <= 1'b0;  else if (all_bits_received == 1'b1)  receiving_data <= 1'b0;  else if (serial_data_in == 1'b0)  receiving_data <= 1'b1; end  always @(posedge clk) begin  prev_receiving_data <= receiving_data;  if (receiving_data==1'b1)  data_received <= 1'b0;  else if (prev_receiving_data==1'b1)  begin  data_received <= 1'b1;  received_data <= data_in_shift_reg[DATA_WIDTH:1];  end end  always @(posedge clk) begin  if (reset == 1'b1)  data_in_shift_reg <= {TOTAL_DATA_WIDTH{1'b0}};  else if (shift_data_reg_en)  data_in_shift_reg <=   {serial_data_in, data_in_shift_reg[(TOTAL_DATA_WIDTH - 1):1]}; end  Baud_Counter RS232_In_Counter ( // Inputs .clk(clk), .reset(reset), .reset_counters(~receiving_data), // Outputs .baud_clock_rising_edge(), .baud_clock_falling_edge(shift_data_reg_en), .all_bits_transmitted(all_bits_received) ); defparam   RS232_In_Counter.BAUD_COUNT= BAUD_COUNT,  RS232_In_Counter.DATA_WIDTH= DATA_WIDTH; /* Altera_UP_SYNC_FIFO RS232_In_FIFO (  // Inputs  .clk (clk),  .reset (reset),   .write_en (all_bits_received & ~fifo_is_full),  .write_data (data_in_shift_reg[(DATA_WIDTH + 1):1]),   .read_en (receive_data_en & ~fifo_is_empty),    // Bidirectionals   // Outputs  .fifo_is_empty (fifo_is_empty),  .fifo_is_full (fifo_is_full),  .words_used (fifo_used),   .read_data (received_data) ); defparam   RS232_In_FIFO.DATA_WIDTH = DATA_WIDTH,  RS232_In_FIFO.DATA_DEPTH = 128,  RS232_In_FIFO.ADDR_WIDTH = 7; */ endmodule module rs232lab(input CLOCK_50, input UART_RXD, inout[7:0] received_data,input [3:0] KEY,output [8:0] LEDG); parameter DATA_WIDTH = 8; //reg [DATA_WIDTH-1:0] received_data; wire RST; assign RST = KEY[0]; wire reset = ~RST; wire receiving_data, data_received; assign LEDG[3] = data_received; assign LEDG[6] = receiving_data; RS232_In u3( // Inputs .clk(CLOCK_50), .reset(reset), .serial_data_in(UART_RXD), // UART_RXD .receive_data_en(1'b1), // Outputs .received_data(received_data), .data_received(data_received), .receiving_data(receiving_data) );  endmodule  can anyone tell me where is my code wrong?

[Altera_Forum]

Maybe you could describe the problem you have first? 

Which hardware do you use? Is this the complete source of your project? Everything in one file?

[Altera_Forum]

Sohail.nadian 

hello can i ask you , do u have now the right code i need it pliz ......... and can you briefly describe what your code do ??? pliz i need it for my project....

[Altera_Forum]

I have another source for using the serial IO. I got this from a friend who used it for a university project. 

The module "serial_out" works as a adapter which reads input data from a FIFO and sends the data in blocks of 8 bit to the TX pin on RS232.  The instantiation is (Verilog):   serial_out instanceSerialOut( .clk_i(iSerialClock), //input clock, 40MHz for 115200 Baudrate .rst_i(iRESET), //reset signal .data_i(InputData), //input data bus, size can be changed inside serial_out .empty_i(FifoEmpty),//signal pin from FIFO, for FIFO is empty signal .req_o(ReadRequest_To_Fifo),//signal pin to FIFO, for read request .txd_o(oTX_Serial)); //pin to UART_TX pin   The data which is read from the fifo is split into blocks of 8 bit each in the serial_out module. Just change the case statement inside the module to the size of the data you read from your fifo.  That should work fine. If you want to run the serial io slower just use half the clock rate. e.g. 20MHz = 57600 Baudrate  cheers, Alex

[Altera_Forum]

Hi beginner, 

 since your post is not related to this thread, could you please delete it and open up a new thread.  Thanks

[Altera_Forum]

To Spellic: He actually should be banned. He posted the same question on five different threads. 

 The guy is not polite and hijacks all theads, regadless of the topic.  I say ban him.

[Altera_Forum]

I need your help to figure out how to connect the PC RS232 to the NIOS UART on a C III starter board. I have a daughter card that exposes the FPGA pins, so I have access physically to ALL I/O pins, Also 5 V and 3.3 V pins on that card. I also have a RS232 to TTL tiny external board that is connected to the PC Serial cable, and has 4 pins as output. The four pins are Power, GND, Tx and Rx. I tried to connect the Tx and Rx to their perspective equal Rx and Tx in the NIOS (pin assignment is correct) after I added the RS232 UART in the nios using SOPC builder, with no flow control. 

 I cannot send or receive on either sides, I mean Nios running c code cannot read or write, the function call stuck. Also on the PC the c code cannot read or write it does also stuck on the function call.  I am using ANSI standard C code for fopen, fgetc, fputc, etc..  Can you help me please to find out how to connect the PC to the UART on the FPGA?  I appreciate it. Thanks.

[Altera_Forum]

update: The code works fine for the DE2-70 board. Just make sure that Quartus does not complain about set-up and hold times. :)  

 i got a de-70 board and realized now that the sample code is not working on it right away. i will try to figure out if it is caused by the different rs232 chip on the board or if my interface causes the problem.  from my perspective the code should be fine. i will post an update once i solved the problem.   Spellic   @Colors: I have no experience with the NIOS stuff, maybe you post your request somewhere else? Besides, I am referring here to the DE2 boards with Cyclone II FPGA. I don't think those two chip family's are compatible.

[Altera_Forum]

Thanks for your info, it's helpful on my project