Unable to assign AltPLL to PLL_L2 in Stratix III (EP3SE260) using Quartus II 9.1

Altera_Forum · ‎02-06-2010

I have a PLL with 4 different frequency outputs clock. I assign this PLL to PLL_L2 & one of this PLL output clocks is assigned to PLL_L2_FB_CLKOUT0p pin. After compiling the project, it automatically changes the assignment to PLL_L3. The pin is assigned correctly. How to lock the PLL assignment so that it will not change to PLL_L3?

Thanks for helping.

Altera_Forum · ‎02-06-2010

Quartus is possibly assigning the PLL location due to the clock input connection. You can add a location assignment in the Quartus Assignment Editor. You have to browse the design hierarchy and locate the actual PLL instance name, like in the below example

set_location_assignment PLL_2 -to "ad9259:adu_control_inst|altpll:ADCLK|pll32_altpll1:auto_generated"

Altera_Forum · ‎02-06-2010

Initially, I assign input clock of PLL to pin_T33(clk1p) or pin_V31(clk0p) and first output clock of PLL to pin_T29(PLL_L2_FB_CLKOUT0p pin) & compile the project. I found out the PLL is assigned to PLL_L3 in the filter report although I have assigned the PLL to PLL_L2 according to Stratix III device pin-out file.

After that, I tried to unassign the input & output clock of this PLL. I add a location assignment for this PLL instance to PLL_L2. But, I can't compile the project successfully. It maybe due to the wrong selection actual PLL instance name? Do you know which filter I should select in node finder so that it can list the actual PLL instance name?

Thanks