Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Unable to generate simulation files for avalon memory mapped read, write and slave IP

Loopback
Beginner
435 Views

I have an existing QPP project, where I want to generate simulation files, so that I can better understand the inter module communication and data flow. I'm getting following errors in the generate dialog box:

 

Error: av_mm_master_wIP_2: av_mm_master_wIP does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.

Error: Avalon_MM_Slave_cIP_0: Avalon_MM_Slave_cIP does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.

Error: av_mm_master_readIP_0: av_mm_master_readIP does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.

 

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sstrell
Honored Contributor III
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What are these?  Is this in Platform Designer?  Where are you seeing these errors?  What exact steps are you following?  More details needed.

Loopback
Beginner
352 Views

Yes, this is in Platform Designer. When I open existing IP in Platform Designer, I go to Generate -> Generate HDL -> simulation model -> Verilog. When I go ahead, I get this error in the Generate dialog box saying, "Generate completed with errors and warnings".

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sstrell
Honored Contributor III
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Then that means whatever these components are, they do not have simulation models available for them.

If these are your own custom components, they need to have Verilog simulation model files specified in the Component Editor when the component is created for this to work.  You can specify the same design files should be used for both synthesis and simulation, but if no simulation model files are specified, you'll get these errors.

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Kenny_Tan
Moderator
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SStrel is right, the error message simply mean it is not supported for simulation.


What IP that you are using in the platform designer? Can you attached your design for us to have a look?


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Kenny_Tan
Moderator
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Not sure if you have update on this?


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Kenny_Tan
Moderator
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As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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