Hello,
Here is the code. After analysis and synthesis i open modelsim from the quartus tool itself, then all the libraries are complied automatically then i click simulate after that i
m getting error posted above.
module led_gpio(clk,user_led,gpio);
input clk;
output [1:0]user_led;
output [3:0]gpio;
reg [31:0] count = 0;
always @(posedge clk)
begin
count <=count+1;
end
assign user_led[0]= count[22]; //user led 1
assign user_led[1]= count[25]; //user led 2
assign gpio[0] = count[20]; //GPIO9
assign gpio[1] = count[4]; //GPIO1
assign gpio[2] = count[30]; //GPIO2
assign gpio[3] = count[31]; //GPIO10
endmodule
So please suggest if any solutions is there.
