Hello
I am using Arria 10 SX and I have in the QSYS Platform design the following IP: Generic Serial Flash Interface Intel FPGA IP
After compilation finished I notice that in the Timing Analyzer – Unconstrained paths – clock Status Summary I have two unconstrained paths of the internal signal of the Generic Serial Flash Interface Intel FPGA IP
The two signals are flash_clk_reg & oe_reg. you can find them in the attach file on line 846 & 847.
The attach file generated by the QSYS (originally it is .sv file)
Do I have to define some constrains?
Is it fine to ignore these unconstrained paths?
All clock above the IP are defined in the sdc file of the design
Thanks Gilad
