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Novice
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Understanding generated RTL from AOC compiler

Hello,

 

Did anyone analyze the verilog/VHDl files after AOC compilation? Which file is the top module. Which files correspond to the OpenCL kernels?

 

Is it possible to optimize the RTL files manually and recompile?

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Valued Contributor II
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The *kernel_name*.v file corresponds to the kernel. There are also a few other .v files in the root of the folder generated by the OpenCL compiler that wrap around the kernel module. The rest of the system is scattered around the sub-folders of this folder. The kernel file itself is 50,000 to 500,000 lines of machine-generated code; modifying it by hand is not very practical.

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You can look at the OpenCL compilation directory for Quartus Synthesis report "top.syn.rpt' to look for all the files used as input to synthesis. It includes all the files including BSP files generated by Platform Designer , Kernel etc.

I agree with @HRZ​  understanding/ optimizing the machine generated files might not be a good idea, you can consider optimizing the Kernel code or write the HDL code from stratch :)

 

Hope this helps.

 

Thanks,

Arslan

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