Unexpected large routing delay on input ports

Altera_Forum · ‎07-31-2012

Hi there,

When constraining some input ports with our design, we observed quite large delay on some ports as follows, most of which is consumed by routing elements.


0.000    0.000                    launch edge time
0.000    0.000                    clock path
0.000      0.000    R                clock network delay
1.000    1.000    F    iExt    1    PIN_AJ32    cpld_gpio
8.747    7.747                    data path
1.000      0.000        RE    1    IOPAD_X0_Y2_N33    STRATIXV_IO_PAD
1.000      0.000        RE    1    IO_PAD_OUTPUT_X0_Y2_N33_I1    IO_PAD_OUTPUT
1.000      0.000        RE    1    IO_INPUT_BUFFER_INPUT_X0_Y2_N34_I0    IO_INPUT_BUFFER_INPUT
1.000      0.000    FF    IC    1    IOIBUF_X0_Y2_N34    cpld_gpio~input|i
1.646      0.646    FF    CELL    8    IOIBUF_X0_Y2_N34    cpld_gpio~input|o
1.646      0.000        RE    1    IOIBUF_X0_Y2_N34    STRATIXV_IO_IBUF
1.646      0.000        RE    1    IO_INPUT_BUFFER_OUTPUT_X0_Y2_N34_I2    IO_INPUT_BUFFER_OUTPUT
1.646      0.000        RE    1    IO_INPUT_PATH_RE_X0_Y2_N52_I0    IO_INPUT_PATH_RE
2.505      0.859        RE    2    IO_INPUT_PATH_RE_X0_Y2_N52_I63    IO_INPUT_PATH_RE
2.505      0.000        RE    1    IO_INPUT_PATH_RE_X0_Y2_N52_I65    IO_INPUT_PATH_RE
2.505      0.000        RE    1    IO_INPUT_PATH_RE_X0_Y2_N52_I57    IO_INPUT_PATH_RE
2.760      0.255        RE    1    IO_RE_X0_Y2_N33_I114    IO_RE
2.796      0.036        RE    1    HIO_BUFFER_X0_Y2_N0_I46    HIO_BUFFER
3.026      0.230        RE    1    C4_X1_Y0_N0_I28    V_SEG4
3.310      0.284        RE    1    R6_X2_Y1_N0_I16    H_SEG6
3.885      0.575        RE    1    C4_X7_Y2_N0_I16    V_SEG4
4.547      0.662        RE    1    C4_X7_Y6_N0_I16    V_SEG4
5.016      0.469        RE    2    C4_X7_Y10_N0_I16    V_SEG4
5.265      0.249        RE    2    R3_X5_Y10_N0_I30    H_SEG3
5.448      0.183        RE    1    C4_X5_Y6_N0_I30    V_SEG4
5.660      0.212        RE    1    C4_X5_Y2_N0_I30    V_SEG4
5.819      0.159        RE    1    C4_X5_Y0_N0_I48    V_SEG4
5.953      0.134        RE    1    R3_X6_Y1_N0_I13    H_SEG3
6.386      0.433        RE    1    C4_X8_Y2_N0_I12    V_SEG4
6.967      0.581        RE    1    C4_X8_Y6_N0_I12    V_SEG4
7.550      0.583        RE    1    C4_X8_Y10_N0_I12    V_SEG4
7.776      0.226        RE    2    R3_X9_Y13_N0_I9    H_SEG3
7.929      0.153        RE    1    R3_X10_Y13_N0_I9    H_SEG3
8.087      0.158        RE    1    R3_X9_Y13_N0_I27    H_SEG3
8.222      0.135        RE    1    R3_X7_Y13_N0_I30    H_SEG3
8.403      0.181        RE    1    C4_X7_Y9_N0_I30    V_SEG4
8.536      0.133        RE    1    LOCAL_INTERCONNECT_X7_Y10_N0_I45    LAB_LINE
8.602      0.066        RE    1    BLOCK_INPUT_MUX_X7_Y10_N0_I65    LEIM_INPUT
8.602      0.000    FF    IC    1    LABCELL_X7_Y10_N48    i_board_services|i_qsys_subsystem|cpld_interface_0|state.flash_mm.readdatavalid~feeder|dataf
8.641      0.039    FF    CELL    1    LABCELL_X7_Y10_N48    i_board_services|i_qsys_subsystem|cpld_interface_0|state.flash_mm.readdatavalid~feeder|combout
8.641      0.000        RE    1    LABCELL_X7_Y10_N48    STRATIXV_LCELL_COMB
8.641      0.000    FF    IC    1    FF_X7_Y10_N49    i_board_services|i_qsys_subsystem|cpld_interface_0|state.flash_mm.readdatavalid|d
8.747      0.106    FF    CELL    1    FF_X7_Y10_N49    board_services:i_board_services|qsys_subsystem:i_qsys_subsystem|cpld_interface:cpld_interface_0|state.flash_mm.readdatavalid

It can be seen that from cpld_gpio[11]~input|o (the input buffer) to state.flash_mm.readdatavalid~feeder|dataf (the register in the code which is directly fed by the input cpld_gpio[11]), there is a delay of 8.602-1.646=6.956ns consumed by routing elements.

Our aim is to constrain the input delay within 5ns and alread have a set_max_delay constraint. We also locate that piece of code close to the input ports in chip planner. However the large delay is still there.

Does anyone know how to efficiently reduce routing delay?

Thanks.

Altera_Forum · ‎07-31-2012

Have you set synthesis tool to use io registers (e.g. through assignment editor) for relevant inputs?

Altera_Forum · ‎07-31-2012

--- Quote Start ---

Have you set synthesis tool to use io registers (e.g. through assignment editor) for relevant inputs?

--- Quote End ---

Thanks. We have enabled the fast input regs. However in our code, the input port actually drives three different register groups in the state machine, like

state 1: reg_A <= cpld_gpio [11];

state 2: reg_B <= cpld_gpio [11];

state 3: reg_C <= cpld_gpio [11];

In this case, even after enabling fast input regs, only one register group will be located next to the I/O port. The other two are still located in the core and have large delay.

Altera_Forum · ‎07-31-2012

I wonder if this going to be any good:

you set the coding to use one io register then assign it to A,B,C

Altera_Forum · ‎07-31-2012

--- Quote Start ---

I wonder if this going to be any good:

you set the coding to use one io register then assign it to A,B,C

--- Quote End ---

That is the problem - we cannot do this. The state machine acts as an avalono-mm interface, and it needs to response the input signal, let's say, wait_request within 1 cycle (or less) by deasserting the read/write signal and sampling the input data. If we use another level of register, the state machine cannot response in time.

Thanks.

Altera_Forum · ‎07-31-2012

in that case remove A,B,C registers and read io register into state machine