Unwanted offset attenuation in FIR filters

[Altera_Forum]

My FIR is now working so far - thanks to Altera Guru "MSchmitt" - but I still have two problems left. Please have a look at the attached pictures - there is an unwanted offset attenuation of 6dB in the filter characteristic. What can I do against that?

[Altera_Forum]

I don't see an indication, that the said 6 dB loss is caused by the FIR filter. But there seems to be a considerable pass band ripple respectively peaking that can't be explained by a FIR filter characteristic. So I guess there's rather a problem with your measurement setup, that hasn't been described in this post (may be otherwhere?). 

 Did you perform a measurement without the FIR filter? Do we see simply the 6dB loss from 50 ohm impedance matching?

[Altera_Forum]

I've added a measurement without a FIR filter in between ADC and DAC - so it seems that 3dB are lost (maybe) in the coneverters - but the remaining 3dB must have to do something with the FIR filter. 

 Loosing exactly half of the signal could indicate a problem with the sign!? - or the converters do not work correctly.  What should I try next?

[Altera_Forum]

--- Quote Start ---  What should I try next?  --- Quote End ---   Depends on what you're trying to achieve, which isn't actually clear from your post. I also don't see, what the shown "miniVNA" is exactly doing. The phase waveform e.g. looks strange, should be a sawtooth rather than a triangle.  To test the FIR filter without the analog signal path, a ModelSim testbench would be the approriate means. Simulation is also the best way to clarify all data type and signal scaling doubts.

[Altera_Forum]

What I want is no additional attenuation besides the filter characteristic. I do not have modelsim, but I can provide some data I collected when trying to find out the exact behavior of the FIR (these are pics from an agilent oscilloscope and the signal tap II logic analyzer). 

 Especially on the pics from the logic analyzer you can see that the output signal of the filter is missing something, occupying only half of the scaling space.

[Altera_Forum]

I agree, that some waveforms look strange. Unfortunately I don't see, how they are achieved. 

 I would expect this: - all filter input/putput/external signals have a signed data type - signed representation is also selected for simulation or SignalTap waveforms - the filter input signal is (almost) DC free, in other words has 0 bias in signed representation

[Altera_Forum]

Everything in this measurements is "unsigned", when there is no other remark. I repeated the whole measurements with everything "signed" and had comparable results (although the permutations were different). I found no combination that worked "right". 

 The filter input signal comes from a Tektronix AFG 3101, and should be completely DC-free. There is nothing in between the devices and instruments exept BNC cables and a "mini circuits" DC-48MHz alias filter at the DAC output.  The miniVNA (vector network analyzer) has 10dB attenuation at each in- and output to protect it - but these are calibrated out.

[Altera_Forum]

Since it is 6dB loss, try multiplying your filter output by 2 i.e. shift one bit to the MSB adding 0 to new lsb. It could be your filter gain implementation is missing one bit.

[Altera_Forum]

I meant "DC free" related to the digital data, signal should be around signed zero with no input. I can't see from your waveforms, if this is the case.

[Altera_Forum]

@kaz: 

Multiplying the FIR filter output with 2 lead to a output signal stuck at GND. I've tried to use the multiply operation before and after the FIR filter.  @FvM: The output signal seems to have no DC component - an average measurement with an Agillent DSO7012A delivered -100µV, while measuruing an aplitude of 206mV. This is strange, because in the Signal Tap II Logic Analyzer, the output signal occupies only one half of the diagrams scaling.  From tomorrow on, I will be on vacation until next week - so don't wonder if my replies do not come in time.

[Altera_Forum]

Without knowing the design and the involved hardware, the question can't be answered I fear. Most Altera ADDA Dev Kits have AC coupled analog I/O, so the output bias doesn't say anything about the digital signal.

[Altera_Forum]

I'm using the following: 

 * DSP Development Kit Stratix III Edition EP3SL150N * HSMC Card with two ADC 14bit and two DAC 14bit * Quartus 8.0 mit SP1 (subscription edition) * mini circuits SLP-50+ alias filter  The design file is attached ...

[Altera_Forum]

The HSMC ADDA card has AC(transformer)-coupled in- and outputs, so it's clear that a possible DC bias does show at the output. 

 The ADC and DAC data representation is unsigned, to process the data without conversion, it's O.K to set the FIR data format to unsigned, as you did. If simulation/SignalTap waveform formats are also set to unsigned, the signal should show centered. The unsigned data representation is only applicable for a low-pass, it wouldn't work for a high-pass or bandpass filter.  Personally I prefer a signed representation for digital signal processing. In this case, the ADC data has to be changed from unsigned (offset binary) to signed (two's complement) by inverting the MSB.  The discussed 6 dB attenuation may be caused by the signal scaling of the ADDA board, but I'm not sure about.

[Altera_Forum]

So, as you say - it should show up centered, but it doesn't ... any idea why? 

 I do not understand why an unsigned input data works only for lowpasses and not for high- or bandpasses. Can you write some words?  I will try now to use a signed representation and post the outcome afterwards.

[Altera_Forum]

I don't know why the signal doesn't show centered. Tracing the signal through the design by simulator or SignalTap should clarify. 

 I must admit, that I'm not using the FIR compiler for filter design yet, so I'm not aware of it's specific operation or possible issues.   Only a lowpass will transmit the input signals DC bias. Assuming the input signal is biased to midscale, it's surely the case for the said ADDA board. A lowpass keeps this property, a bandpass or highpass will have zero output bias, unless you apply an artificial offset. (I don't assume that the FIR compiler does for unsigned designs).  When changing the filter design to signed (my preferred representation for DSP), you have to change the AD data from offset binary to two's complement by inverting the MSB, and vis-versa for the DA output.

[Altera_Forum]

Because the FIR output looks correct (except for a possible offset), it seems clear that the above internal signal has a wrong display format.  

 The reason for the apparent offset is still unclear to me. Would you mind to post a quartus archive (*.qar file) of the full test design, including filter parameters and signal tap definition?

[Altera_Forum]

No problem :D.

[Altera_Forum]

I see, that the original (unsigned) filter design implements a DC gain of 0.57 (sum of integer coefficients = 1167, scaling factor = 2048). This is, what you see as an offset in the unsigned SignalTap. The input data is centered to midscale (8192), the output data to about 4650. 

 If you use signed data representation throughout the design, the data should stay zero biased when passing the filter, but still attenuate the signal level. The arbitrary gain is apparently a result of the FIR compiler's scaling method, depending on the number of coefficients.

[Altera_Forum]

I thought I was using only signed representations, when switching the pulldown in the FIR comiler to "signed" - so, this is obviously not the case - what do I have to do in addition? 

 :confused::confused::confused:  So, if the arbitrary gain is a result of the number of coefficients - what number would you suggest to get optimal results? Would it be a good idea to switch from "auto scaling" maybe to e.g. "auto scaling to power 2"? Under what conditions?

[Altera_Forum]

I basically wanted to report, that the attenuation is introduced by the FIR compiler. I didn't check the options to change this behaviour, it should be discussed in the FIR compiler manual. As I said, I don't use the tool in my designs yet. But I expect, that you can basically achieve a gain of 1. 

 I also didn't check the implications of using different number represenation with the FIR tool. I just told, how it should be according to usual DSP practice. Apparently, the ADC number format can be switched in your ADDA hardware, otherwise the MSB has to be inverted, most likely necessary for the DAC.

[Altera_Forum]

I'm not an expert but wonder if you are able to simulate your digital filter behaviour. 

If running a simulation with a constant input, you see it lowered, then it depends on the FIR filter.  Further the simulation can tell you which is the correct format of the output (MSB representation etc.)  Otherwise, can it be the DAC?  hope this helps.