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Hi there,
Most of our design projects are still on QII 9.1 SP2 and we are looking to upgrade them to the latest and greatest. One problem we found in this migration process, is the resource usage of the same design increased significantly (>10%), which caused one of the projects fail to fit in newer Quartus II (it was more than 90% full when compiled with QII 9.1 SP2, but it fits). Does anyone else see this problem? If this is common, are there any solutions available to make the design fit again after migrating to newer Quartus II? BTW, we pretty much used all the design advices in QII 9.1 SP2 for resource optimization, could it be that some of the optimization settings got removed in the newer versions to cause this? Thanks! HuaСсылка скопирована
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--- Quote Start --- Most of our design projects are still on QII 9.1 SP2 and we are looking to upgrade them to the latest and greatest. --- Quote End --- You can't for some devices, eg., FLEX10K and ACEX series devices. I use a VirtualBox virtual machine installation for these devices. --- Quote Start --- One problem we found in this migration process, is the resource usage of the same design increased significantly (>10%), which caused one of the projects fail to fit in newer Quartus II (it was more than 90% full when compiled with QII 9.1 SP2, but it fits). Does anyone else see this problem? If this is common, are there any solutions available to make the design fit again after migrating to newer Quartus II? BTW, we pretty much used all the design advices in QII 9.1 SP2 for resource optimization, could it be that some of the optimization settings got removed in the newer versions to cause this? --- Quote End --- I don't recall seeing anything dramatic when changing Stratix II device designs to newer versions, other than in 10.1 the Classic Timing Analyzer is gone, so you have to use TimeQuest. Generate a Tcl file for your project under 9.1SP2 and look at the settings. Do the same under the newer version, and see what is missing. Cheers, Dave
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Thanks Dave. The project we are concerned about is on Cyclone III (3C25), and we don't use classic timing analyzer. Will try out the tcl file idea though.
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--- Quote Start --- The project we are concerned about is on Cyclone III (3C25), and we don't use classic timing analyzer. Will try out the tcl file idea though. --- Quote End --- The DE2 uses a Cyclone III device. Look at the de2_basic.zip file in this thread: http://www.alteraforum.com/forum/showthread.php?t=33462 The design uses a Tcl script for synthesis. You can use that to get ideas for your own script. You can use Quartus to generate a Tcl file for your project and compare it to this script to see how the Tcl procedures can be rearranged. Cheers, Dave

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