Uploading FPGA configuration

[Altera_Forum]

Hi 

 I'd like to know if it is possible to upload a newly programmed configuration from a FPGA? I use the Quartus II 9.1 SP1 to program a .sof and .pof file into a FPGA. Is there any way that I can recover these .sof and .pof files from the FPGA?   Apologies in advance for this noob question.   Thanks, alteraQuartusUpload

[Altera_Forum]

No, there is no support for reading back either an .sof or .pof (other than the .pof verify option, but that does not give you an option to save to file). 

 Cheers, Dave

[Altera_Forum]

Thanks for the quick response, Dave. I'm principally looking for a way to verify that the Quartus II programmer actually programmed the files in and was hoping that there might be a way to read back the files and then do a compare between these two files. *sigh* Perhaps there is another software that can do this? 

 Thanks, alteraQuartusUpload

[Altera_Forum]

--- Quote Start ---  Thanks for the quick response, Dave. I'm principally looking for a way to verify that the Quartus II programmer actually programmed the files in and was hoping that there might be a way to read back the files and then do a compare between these two files. *sigh* Perhaps there is another software that can do this?   --- Quote End ---    The .pof has a verify option.  The .sof will fail to configure the device if there was an error.  If your JTAG cable is good, you should not have any problems with configuring the devices.  Cheers, Dave

[Altera_Forum]

If the files did not program in, then the Cong_done should not go high, and the nSTATUS should go low. (assuming you have pull up resistors on them. 

 Optionally, you can also program a user IO pin to be INIT_DONE, and this will only go high after the FPGA is fully loaded, and has transitioned through Initialization into User Mode (the user design is now running on the FPGA).

[Altera_Forum]

I experimented a bit, it is possible to upload the .pof file from the FPGA using the Examine feature in the Quartus II Programmer. This works perfectly, to compare the downloaded and uploaded .pof files. But there seems to be no way to upload the .sof file.  

 I'm most interested in verifying if the correct files were programmed in, not the status of the FPGA after programming.   "The .sof will fail to configure the device if there was an error. -- Dave" : Do you mean if there was an error in the FPGA loading the .sof file then there would be an expected configuration error?

[Altera_Forum]

--- Quote Start ---  I experimented a bit, it is possible to upload the .pof file from the FPGA using the Examine feature in the Quartus II Programmer. This works perfectly, to compare the downloaded and uploaded .pof files.   --- Quote End ---    Ok, that's good to know. I use the JAM STAPL player verification option to confirm that EPC2 EEPROMs have been loaded with the .pof I expect.    --- Quote Start ---   But there seems to be no way to upload the .sof file.    --- Quote End ---    Arguably, there's no need. If the FPGA is configured from a device loaded with a .pof, and you can confirm that .pof is correct, then the loaded FPGA will also be correct. The .sof is just another version of the .pof, but used by JTAG download.    --- Quote Start ---   I'm most interested in verifying if the correct files were programmed in, not the status of the FPGA after programming.    --- Quote End ---    If you're worried about a production board being loaded with the wrong configuration, then you should really have software read a hardware register. For example, I'll often have board ID, design ID, version, and timestamp registers. I also use pull-ups/downs on external pins to indicate a board revision. That way each .sof can enable functionality once they check they are loaded into the correct hardware.    --- Quote Start ---   "The .sof will fail to configure the device if there was an error. -- Dave" : Do you mean if there was an error in the FPGA loading the .sof file then there would be an expected configuration error?  --- Quote End ---    If you have a bad JTAG connection, and your .sof download gets corrupted, then the FPGA will detect the error and drive the nSTATUS configuration pin low to indicate failure.  Cheers, Dave

[Altera_Forum]

Thanks Dave, 

 So much of htis is hard to detail out and a new user has no clue at wherei n the Altera documentation it is all explained, and how it all inter-relates.  Some is in the device handbook, other stuff is in the Configuration handbook.  But, as I have often observed, "It is perfectly clear once you understand it".  Learning all the terms, while also trying to apply them in context is quite difficult.  We hope this helps - alteraQuartusUpload.  Avatar

[Altera_Forum]

--- Quote Start ---   Some is in the device handbook, other stuff is in the Configuration handbook.   --- Quote End ---    I've given up reading books ... I put myself to sleep reading handbooks, datasheets, and user manuals :)  Cheers, Dave

[Altera_Forum]

Thanks for your helpful response, Dave and Avatar. Appreciate it!.  

 alteraQuartusUpload

[Altera_Forum]

I am wondering if we can read Jic file from EPCS flash devices 

   --- Quote Start ---  Ok, that's good to know. I use the JAM STAPL player verification option to confirm that EPC2 EEPROMs have been loaded with the .pof I expect.       Arguably, there's no need. If the FPGA is configured from a device loaded with a .pof, and you can confirm that .pof is correct, then the loaded FPGA will also be correct. The .sof is just another version of the .pof, but used by JTAG download.       If you're worried about a production board being loaded with the wrong configuration, then you should really have software read a hardware register. For example, I'll often have board ID, design ID, version, and timestamp registers. I also use pull-ups/downs on external pins to indicate a board revision. That way each .sof can enable functionality once they check they are loaded into the correct hardware.       If you have a bad JTAG connection, and your .sof download gets corrupted, then the FPGA will detect the error and drive the nSTATUS configuration pin low to indicate failure.   Cheers, Dave  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  I am wondering if we can read Jic file from EPCS flash devices  --- Quote End ---    You can read the contents of the flash easily enough. Its just SPI flash.  You can instantiate an SPI controller or just PIO and access the flash directly. You just need to set the EPCS interface pins as "Use as regular I/O" so that you can connect them to your custom logic.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I am wondering if we can read Jic file from EPCS flash devices  --- Quote End ---   Please do not multipost. You already asked the question here (http://www.alteraforum.com/forum/showthread.php?t=37791) and even got an answer!