Usage of negative edge trigger for dual clock RAM

[BDarji]

Dear all,

Greetings of the Day!

We are having one dual port RAM with separate clock for port A and Port B. Port B related signals are driven within FPGA. While port A related signals will be driven from outside FPGA. Now, external processor which will be driving port A is generating signals based on negative edge of clock.

So, we are thinking to use always @ (nedgedge clk_a) for all logic related to port A while using always@ (posedge clk_b) for all logic related to port B.

For example,

// Port A 
// Note that in following we have used negative edge.
  always @ (negedge clk_a)
    begin
      if (we_a) 
        begin
          ram[addr_a] = data_a;
        end
      q_a <= ram[addr_a];
    end 

// Port B 
  always @ (posedge clk_b)
    begin
      if (we_b) 
        begin
          ram[addr_b] = data_b;
        end
      q_b <= ram[addr_b];
    end

1. Would Quartus be happy to implement this and infer memory block for this?
2. Can this have any impact on achieving timing requirements for port A?
   1. clk_a and clk_b both are asynchronous so we do not need to worry about timing across domain.

Please feel free to let me know if any further information is needed.

Thank you,

Bhaumik

[_AK6DN_]

Since the signals for port A are derived from an external source, why just not add an inversion to
flip the (external) negative clock edge to an (internal) positive clock edge? The signals have to go
thru I/O drivers and logic to get on chip anyway, so it will cost you effectively nothing, and make
the design much more straightforward, a standard posedge referenced ram block on both ports.

[BDarji]

Hello,

Thank you for answer.

Let me try to give more information.

In above image, external DSP is driving chip select, write request, address and data. Based on those signals, we should perform memory write operation. I have also shown some internal signals which we are planning to derive from above and then pass it to memory. 

As DSP is driving signals out on negative edge of clock, I thought it would be good to use negative edge itself. 

You mentioned that clock should be inverted. If we invert clock, will not it effect timings?

Please let me know if my understanding is wrong.

Have a Nice Day!

Regards,

Bhaumik

[Nurina]

Hello,

Thank you for using Intel Communities.

I have tried your original proposed design on Quartus 22.1std. Here are my answers to your questions:

1) Would Quartus be happy to implement this and infer memory block for this?

• Yes, the RAM is inferred when I tried this.

2) Can this have any impact on achieving timing requirements for port A?

• Let me check with my team first and get back to you on this.

Regards,

Nurina

[Nurina]

Hi,

Based on timing reports it should be fine to use negedge trigger as you proposed.

I've also done RTL simulation and it works as expected.

Posedge:

Negedge:

Regards,

Nurina

[BDarji]

Hello Nurina,

Thank you for your response.

Kind Regards,

Bhaumik

[Nurina]

Hi Bhaumik,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Have a great day!

Best regards,

Nurina W.