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SS5
Novice
774 Views

Using AVALON FIFO MEMORY CORE : Data are Repeating in NIOS

Hello,

I am generating Trigger (500ns) and Counter data using Verilog code, whereas at every positive edge of trigger i am collecting and storing the data in register.

Verilog code

module Counter( input clk, input enable, input reset, output reg[31:0] Final_value, output reg trig ); reg[31:0] counter_out; reg [7:0] temp=0; reg [31:0] counter_result; wire temp1; wire edge_detect;   always@(posedge clk) begin if(reset) begin trig<=0; temp<=0; counter_out<=0; end else if (enable==1'b1) begin counter_out<=counter_out+1; temp<=temp+1; if(temp==25) begin temp<=0; trig<=~trig; end end end assign temp1=trig; assign temp2=temp1&&clk; always@(posedge temp2) if(reset) counter_result<=0; else begin counter_result<=counter_result+1; end always@(posedge trig) if(reset) Final_value<=0; else begin Final_value<=counter_result; end endmodule

Altera Design as follows

  1. Counter module changed into block
  2. Interconnected with Qsys component
  3. Using FIFO, try to read the counter data
  4. Verifying the result in NIOS

Top design

FIFO_Trig.JPG

QSYS

Qsys_FIFO.JPG

IN NIOS , Data is repeating . I dont know why. can anyone please suggest me. Whether Verilog code logic is right.

NIOS_console.JPG

0 Kudos
1 Reply
Ahmed_H_Intel1
Employee
29 Views

Hello,

Can you please review this part of code:

  1. always@(posedge clk)
  2. begin
  3. if(reset)
  4. begin
  5. trig<=0;
  6. temp<=0;
  7. counter_out<=0;
  8. end
  9. else if (enable==1'b1)
  10. begin
  11. counter_out<=counter_out+1;
  12. temp<=temp+1;
  13. if(temp==25)
  14. begin
  15. temp<=0;
  16. trig<=~trig;
  17. end
  18. end
  19. end

 

I see that after the first count is over if the reset signal didn't come the trig will stay high and there will be two counters are counting at the same time because (assign temp1=trig;) temp1 will be high and then the next counter will be enabled and counting with the clk

  1. always@(posedge temp2)
  2. if(reset)
  3. counter_result<=0;
  4. else
  5. begin
  6. counter_result<=counter_result+1;
  7. end
  8. always@(posedge trig)
  9. if(reset)
  10. Final_value<=0;
  11. else
  12. begin
  13. Final_value<=counter_result;
  14. end

 

I recommend to remove this assignment and try again

assign temp2=temp1&&clk;

 

or to change it to

assign temp2=temp1;

 

I know this isn't the desired system but just for debugging

 

 

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