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Hello all,
I am using a Cyclone 3 device with an altera serial configuration device. The configuration device uses 3.3 volts and so the board was designed with a VCCIO of 3.3 volts for the associated FPGA pins. The issue is that when using the serial flash loader with the quartus software the SFL pins are forced to configure as the 2.5 standard. For my purposes I am able to eliminate all other 3.3 v IO in bank 1 from the design and allow the bank to be configured for 2.5 volts so that the design will compile. However, I am worried that there could be negative side effects caused by configuring the bank as 2.5 but supplying VCCIO with 3.3 V. Does anyone know whether this could cause a problem?Link Copied
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I'm not quite sure, if it's still required by the Quartus software, but I did the same for various reasons. In my understanding, the bank voltage information is mainly used to check pin placement rules and to map the IO-strength/pin impedance settings to physical driver settings. If you care to keep the maximum voltage/current requirements according to the real bank voltage, no problem should exist.
Some EPCS devices are possibly working also at 2.5V supply, e.g. those EPCS4 exemplars, that identify as Numonyx M25P40 by their electronic signature.
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