Using create_generated_clock on an input clock of source sync DDR

[Altera_Forum]

Altera Experts, I have a timing question on a source synchronous interface (of course!) 

 I'm trying to talk to a high speed ADC. It accepts a 33MHz clock, ramps it up and sends out a 200MHz data clock, a 33MHz frame clock and the data via a DDR interface. The 33MHz input clock comes from a Stratix III FPGA. I know the board delay for the 33MHz clock there, and the 200MHz and frame clock back. The datasheet tells me the relationship between the clocks in the ADC chip. (Tpd) Can I constrain 200MHz clock to the 33MHz FPGA clock? What about constraining the 200MHz and frame clock together? What is the best way to do this?  method A)# ####### create_clock -name inclk_33MHz -period 30 [get_ports {master_clock[0]}] derive_pll_clocks # output of the pll PLL_core|Inst_pll|altpll_component|auto_generated|pll1|clk[0] is the pin of the PLL that I'm using   create_generated_clock -name ADCclk_out   -source [get_pins {PLL_core|Inst_pll|altpll_component|auto_generated|pll1|clk[0]}]   -add   [get_ports {samplingclock}] # Ok, I'm not sure this is required, but what I'm trying to do is constrain the path from the PLL pin to the output port on the FPGA# My thinking is that derive_pll_clocks will constrain to the output pin of the PLL and not further.# I need quartus to know about this delay because of the next constraint...  create_generated_clock -name DCO_200MHz   -source [get_ports samplingclock]   -multiply_by 6   -offset 4.071   -add   [get_ports {DCO}] # Ok, here is my thinking behind this one, I can tell quartus, that I have this input (DCO), that is related to samplingclock (the output port on the FPGA), but it is 6 times as fast and is offset by 4.071 ns {board delay there + Tpd in ADC + board delay back}  create_generated_clock -name FCO_33MHz   -source [get_ports samplingclock]   -offset 3.085   -add   [get_ports {FCO}] # same as DCO, but without the -multiply_by and a different offset # I want to tell quartus, "look this input is just like that output, except it is delayed by 3.085ns"# I've never seen any examples of using create_generated_clock on an input, so I'm guessing it is wrong.  method B)# ####### create_clock -name inclk_33MHz -period 30 [get_ports {master_clock[0]}] create_clock -name FCO_33MHz -period 30 -waveform {0 15} [get_ports {FCO}] create_clock -name DCO_200MHz -period 5 -waveform {0.986 3.486} [get_ports {DCO}]  derive_pll_clocks set_clock_groups -asynchronous -group{DCO_200MHz FCO_33MHz} # ignore the fact that inclk_33MHz and {DCO_200MHz FCO_33MHz} are related in anyway and treat them as asynchronous# by using -waveform, I can still relate FCO_33MHz and DCO_200MHz together from the delay I calculated above {board delay there + Tpd in ADC + board delay back}    So, what do you think? Am I being a fool to think that I can relate these two clocks? I have four of these types of ADCs, and they all get their input 33MHz clock from the same source, the FPGA, so I'd like to relate them instead of having a bunch of different clock domains.

[Altera_Forum]

Hi, 

I was wondering what your solution was to this problem. I have the same clock feedback from the ADC issue and I'd like to tie the clock from ADC to the clock I generate.  Thanks.    --- Quote Start ---  Altera Experts, I have a timing question on a source synchronous interface (of course!)  I'm trying to talk to a high speed ADC. It accepts a 33MHz clock, ramps it up and sends out a 200MHz data clock, a 33MHz frame clock and the data via a DDR interface. The 33MHz input clock comes from a Stratix III FPGA. I know the board delay for the 33MHz clock there, and the 200MHz and frame clock back. The datasheet tells me the relationship between the clocks in the ADC chip. (Tpd) Can I constrain 200MHz clock to the 33MHz FPGA clock? What about constraining the 200MHz and frame clock together? What is the best way to do this?  method A)# ####### create_clock -name inclk_33MHz -period 30 [get_ports {master_clock[0]}] derive_pll_clocks # output of the pll PLL_core|Inst_pll|altpll_component|auto_generated|pll1|clk[0] is the pin of the PLL that I'm using   create_generated_clock -name ADCclk_out   -source [get_pins {PLL_core|Inst_pll|altpll_component|auto_generated|pll1|clk[0]}]   -add   [get_ports {samplingclock}] # Ok, I'm not sure this is required, but what I'm trying to do is constrain the path from the PLL pin to the output port on the FPGA# My thinking is that derive_pll_clocks will constrain to the output pin of the PLL and not further.# I need quartus to know about this delay because of the next constraint...  create_generated_clock -name DCO_200MHz   -source [get_ports samplingclock]   -multiply_by 6   -offset 4.071   -add   [get_ports {DCO}] # Ok, here is my thinking behind this one, I can tell quartus, that I have this input (DCO), that is related to samplingclock (the output port on the FPGA), but it is 6 times as fast and is offset by 4.071 ns {board delay there + Tpd in ADC + board delay back}  create_generated_clock -name FCO_33MHz   -source [get_ports samplingclock]   -offset 3.085   -add   [get_ports {FCO}] # same as DCO, but without the -multiply_by and a different offset # I want to tell quartus, "look this input is just like that output, except it is delayed by 3.085ns"# I've never seen any examples of using create_generated_clock on an input, so I'm guessing it is wrong.  method B)# ####### create_clock -name inclk_33MHz -period 30 [get_ports {master_clock[0]}] create_clock -name FCO_33MHz -period 30 -waveform {0 15} [get_ports {FCO}] create_clock -name DCO_200MHz -period 5 -waveform {0.986 3.486} [get_ports {DCO}]  derive_pll_clocks set_clock_groups -asynchronous -group{DCO_200MHz FCO_33MHz} # ignore the fact that inclk_33MHz and {DCO_200MHz FCO_33MHz} are related in anyway and treat them as asynchronous# by using -waveform, I can still relate FCO_33MHz and DCO_200MHz together from the delay I calculated above {board delay there + Tpd in ADC + board delay back}    So, what do you think? Am I being a fool to think that I can relate these two clocks? I have four of these types of ADCs, and they all get their input 33MHz clock from the same source, the FPGA, so I'd like to relate them instead of having a bunch of different clock domains.  --- Quote End ---