Using multiple BFMs in VHDL / Problems with use clauses

[Altera_Forum]

Hi. 

 I'm trying to create a VHDL testbench using Altera Verification BFMs.  The DUT has an Avalon-MM Slave Interface, an Avalon-ST Sink Interface and an Avalon-ST Source Interface. The generated QSYS system has an Avalon-MM Master BFM, an Avalon-ST Source BFM and an Avalon-ST Sink interface.  I can't make it work when I use more than one interface.  Consider this [simplified] example:   library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library bfm_test_mymodulesink_bfm; use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all; <entity declaration> <architecture declaration> process is begin set_transaction_channel(channel, id, req_if(id)); set_transaction_data(data, id, req_if(id)); push_transaction(id, req_if(id)); end process;   This works fine and I'm able to see the Source BFM sending data to my module Sink Interface in ModelSim waveform window.  However, I can't make it work when I try another interface.  If I ->  1) Don't insert any library / use clause in the VHDL file: ModelSim complains it can't find the functions. [That's expected]. This happens even if I write them in the form library.package.function_name.  2) Insert both libraries + use clauses at the beginning of the VHDL file: ModelSim doesn't know from which library it should use the functions.  library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library bfm_test_mymodulesink_bfm; use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all; library bfm_test_mymodulesource_bfm; use bfm_test_mymodulesource_bfm.altera_avalon_st_sink_bfm_vhdl_pkg.all; library bfm_test_mymoduleavmm_bfm; use bfm_test_mymoduleavmm_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.all; <entity declaration> <architecture declaration> process is begin set_transaction_channel(channel, id, req_if(id)); set_transaction_data(data, id, req_if(id)); push_transaction(id, req_if(id)); end process;  # ** Error: ./../teste_bfm_sys_tb.vhd(568): (vcom-1078) Identifier "req_if" is not directly visible.  [That's also expected]. However if I use the full name, as in library.package.function, I still get an error:  bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.req_if(0)  # ** Error: ./../teste_bfm_sys_tb.vhd(568): Illegal expanded name prefix ("bfm_test_mymodulesink_bfm" is not label of block, process, generate, or (for) loop statement).# ** Error: ./../teste_bfm_sys_tb.vhd(568): (vcom-1195) Cannot find expanded name "bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg". [This should work, if I'm not mistaken].  3) Insert both libraries at the top of the file, and the use clauses in separate process (that's what the example test_program_pkg.vhd provided by Altera also does):  library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library bfm_test_mymodulesink_bfm; --use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all; library bfm_test_mymodulesource_bfm; --use bfm_test_mymodulesource_bfm.altera_avalon_st_sink_bfm_vhdl_pkg.all; library bfm_test_mymoduleavmm_bfm; --use bfm_test_mymoduleavmm_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.all; <entity declaration> <architecture declaration> source_bfm_process : process is use bfm_test_mymodulesink_bfm.altera_avalon_st_source_bfm_vhdl_pkg.all; begin set_transaction_channel(channel, id, req_if(id)); set_transaction_data(data, id, req_if(id)); push_transaction(id, req_if(id)); end process source_bfm; <processes for sink / master>   I get the same error as in (2).  "Illegal expanded name prefix" "Cannot find expanded name" / "Unknown expanded name".   Could anybody explain to me what I'm doing wrong? What's the proper way to instantiate the provided BFMs functions in VHDL testbenches?

[Altera_Forum]

--- Quote Start ---   Could anybody explain to me what I'm doing wrong? What's the proper way to instantiate the provided BFMs functions in VHDL testbenches?   --- Quote End ---   I haven't tried using the VHDL BFMs, but in my experience, Altera's msim_setup.tcl scripts suck.  1. Look in msim_setup.tcl  msim_setup.tcl suckiness#1: Altera names the library it compiles the HDL component into after its Qsys name. This is stupid, since if I have a Qsys design with three component instances, then I end up with three separately named libraries.  Are the packages you are trying to use actually getting compiled into the libraries you are referencing? If not edit msim_setup.tcl to reflect the libraries you want to use. This solution is annoying, since you need to edit msim_setup.tcl each time you regenerate the Qsys system.  2. Default bindings  Its quite possible that you could exploit a Verilog feature of Modelsim to work around what may be an issue with. The vsim -L option can be used to tell Modelsim which libraries to search for default bindings. As long as your HDL code has a component declaration, then the component should resolve to the last instance compiled (which is in one of the libraries referenced by -L).  If none of these ideas pan out, try and post a minimal set of code, along with a text file of what you are trying to do, and I'll take a look.  I posted a SystemVerilog design that uses the BFM master and slave here (see Post#25);  http://www.alteraforum.com/forum/showthread.php?t=32952&page=3  Read through that and perhaps that has a solution too, eg., you could create your simple design in Verilog, and then again in VHDL. It should be possible to get the same functionality working with either language.  Note: as far as HDL languages go, I'm more familiar with VHDL. The reason I wrote the BFM test in SystemVerilog is that the VHDL BFM is only a recent addition to the test suite.  Cheers, Dave

[Altera_Forum]

I made it work the "dumb" way: 

 >Include all altera_BFM libraries and use clauses for the testbench entity >Rename the conflicting signals (such as req_if) or functions in the BFMs files (altera_avalon_master_bfm_vhdl_*, etc) so the compiler will know exactly which one you're calling >Done  It's a workaround, I still don't know why ModelSim won't allow me to restrain the use clauses to specific processes or to use the functions with the syntax library.package.function().