When I attempt to compile the following snippet of code with Quartus 20.1.1 Lite I get an error that it does not recognize the $error() function added in System Verilog 2009. Does the lite version of Quartus Prime support System Verilog 2009? I don't see the option in my project settings to specify which version of System Verilog to use (see attached screenshot). Intel documentation states that Quartus 20.1 works with 2005, 2009, and 2012, but StackOverflow states that this is only the case with the Prime Pro versions.
Can anyone confirm that Quartus Prime Lite does support System Verilog 2009 for me?
generate if(8 % 3 != 0) begin $error("8 is not evenly divisible by 3"); end endgenerate
Error (10170): Verilog HDL syntax error at adc_data_buffer.sv(17) near text: "$error"; expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "adc_data_buffer" at adc_data_buffer.sv(2) due to previous errors
Thank you for the clarification. It looks like Quartus Prime Pro has supported System Verilog 2009 since at least version 17.0 . When you say "at the moment", do you know if there is a roadmap that you can share regarding when support for SV 2009 may be targeted for Quartus Prime Lite?
Just to let you know that our engineering team are now focusing on feature enhancement/bug fixing on the Pro edition. For Lite edition, they will put this as lower priority. We are sorry to inform this.
With that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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