VCS error Error-[URMI] Unresolved modules in cyclonev_atoms_ncrypt.v

[eman_delete]

I'm trying to run the vcsmx_setup.sh script generated by QSYS. I'm getting the elabortion error:

Error-[URMI] Unresolved modules

/<path>/quartus_15.0/quartus//eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v, 25

I'm not able to understand which module is missing since cyclonev_atoms_ncrypt.v is protected.

I tried different ways to resolve this error, based on different documentation materials, e.g. trying the exact vcs version supported by quartus_15.0, using -lca flag and 64bit version, no -v for the altera_lnsim.v compilation, etc.

I also tried to use the unencrypted cyclonev_atoms.v file. Even for this file I can see that the following encrypted module is instantiated and is missing 

cyclonev_clk_phase_select_encrypted

I'm trying to understand which way should I proceed? Should I continue with the encrypted file?

In this case, how can I find which module is missing? Should I continue with the unencrypted file?

In this case, where can I find the cyclonev_clk_phase_select_encrypted module?

Is it correct that the _atoms_ files are for the netlist simulation? I'm trying to simulate RTL, why these files are in the QSYS generated .sh script? Is it because, some of the models are netlist?

If so, I cannot just remove these files from the compilation list, can I?

[SyafieqS]

Hi Eugene,

First of all, is it possible for you to migrate to at least supported version of Quartus?

I can see you are using 15 which has been eol-ed.

If this is the issue, I am afraid it is hard to support.

Let me know the concern on this.

[SyafieqS]

Let me know if there is any update or concern from previous reply

[eman_delete]

Hello,

The issue isn't resolved. I cannot upgrade to a newer version of quartus.

Thank you.

[SyafieqS]

Just for sanity check, can you try to recompile and generate everything. Then compile and run the script again it to see if the issue still appear? 

[eman_delete]

The model's code was genrated and regenerated in Qsys multiple times.

None of the attempts solved the problem. 

[SyafieqS]

Is that possible for you to attach the design here?

Since Quartus 15 is hard to support as it had been eol-ed, I will take a look at it.

Let me know any concern on this.

[eman_delete]

Thank you.

Please find the testcase attached.

If you have vcs installation you can reproduce the issue by extracting the file, setting  PATH, VCS_HOME, license and  QUARTUS_INSTALL_DIR in the vcsmx_setup.sh file, and running the commands:

cd testcase_quartus15/simulation/synopsys/vcsmx

./vcsmx_setup.sh | tee log.log

Please let me know if you are able to see the elaboration error:

Error-[URMI] Unresolved modules
/QUARTUS_INSTALL_DIR/quartus//eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v, 25

In the attached file you can find my log.log with all the compilation and elaboration messages.

[SyafieqS]

Massive thanks. I will take a look at it and let you know any update

[SyafieqS]

I am further investigate this. Will let you know any update.

[RichardTanSY_Altera]

Have you try the Nativelink feature in the Quartus Standard?

You can try to simulate using the Nativelink feature to automatically compile your design, Intel IP, simulation model libraries and testbench.

Best Regards,

Richard Tan

[eman_delete]

Hi,

I provided a testcase. 

The provided testcase is a Qsys block and it cannot be simulated by using the scripts generated by Qsys.

This block is a part of a bigger Quartus project, where I do have the NativeLink option. How the bigger project can be simulated when one of its blocks has issues?

Thank you.

[SyafieqS]

Hi,

What meant by that is using nativelink method in Quartus, for the submodule and see if it is able to simulate instead of using current method.  You might need to try and see the if it is possible.

[eman_delete]

I gave it a try. I created a project using the qip file from the qsys block.

The project was successfully analyzed and elaborated in Quartus. The 3-rd party simulation scripts were generated.

I executed the generated tcl file:

   quartus_sh -t balmas_exmple_vcsmx_rtl_verilog.tcl

I got the message that the compilation was successful. I didn't get anything about the elaboration.

Then I tried to elaborate the design using the command:

  vcs -debug_access+all nios_sys -kdb -lca

I'm getting a different type of errors. During the design elaboration I see multiple errors:

Error-[UPIMI-E] Undefined port in module instantiation
/<project path>/quartus_prj_nios_sys_only/nios_sys112_verilog/synthesis/submodules/alt_mem_ddrx_controller.v, 1072
Port "local_zqcal_req" is not defined in module 'alt_mem_ddrx_input_if'
defined in
"/<installation path>/quartus_15.0/quartus/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v",
25
Module instance: alt_mem_ddrx_input_if
#(.CFG_LOCAL_DATA_WIDTH(CFG_LOCAL_DATA_WIDTH),
.CFG_LOCAL_ID_WIDTH(CFG_LOCAL_ID_WIDTH),
.CFG_LOCAL_ADDR_WIDTH(CFG_LOCAL_ADDR_WIDTH), .CF ...

I can downgrade severity of these errors (-error=noUPIMI-E) , but I cannot downgrade/suppress the errors:

Error-[TMIPC] Many port connections
/<project path>/quartus_prj_nios_sys_only/nios_sys112_verilog/synthesis/submodules/alt_mem_ddrx_controller.v, 1321
Too many module or UDP instance port connections:
Too many port connections are found for instance "tbp_inst" of module
"alt_mem_ddrx_tbp"
Source info: alt_mem_ddrx_tbp #(.CFG_CTL_TBP_NUM(CFG_CTL_TBP_NUM),
.CFG_CTL_SHADOW_TBP_NUM(CFG_CTL_SHADOW_TBP_NUM),
.CFG_ENABLE_SHADOW_TBP(CFG_ENABLE_SHADOW_TBP), .CFG_DWI ...
Module "alt_mem_ddrx_tbp" is defined at
"/<installation path>/quartus_15.0/quartus/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v",
25

I see 4 errors and all of them are from the same encrypted file:

/<installation path>/quartus_15.0/quartus/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v

[SyafieqS]

Hi,

Did you able to simulate in latest version of Quartus?

And see if this resolve the issue with nativelink flow

[SyafieqS]

Let me know if there is any update from your end

[eman_delete]

Hello,

I have already replied in this thread that I cannot upgrade the used  Quartus version. I has to use Quartus 15.0.

Anyway, after multiple attempts and exeperiments, I was able to find the name of the unresolved module.

The missing module is asmi_sim_model. If I stub this module I'm able to elborate the Qsys model.

I can see the following information on how to use the asmi model:

https://www.youtube.com/watch?v=kxNDMSUQt1Q

I also read the article: ASMI_an720-683464-667011.pdf

What should be the approach if I want the capability of running simulation of the full chip including SW (NIOS), DDR, TSE, SGDMAs, QSYS interconnect and other modules in the design? Can it be done without the Flach BFM models? Should I stub the asmi_sim_model, or is there a better solution?

Thank you.