Re: VHDL Compilation problem : Quartus 11 : Error (12061):

Altera_Forum · ‎08-07-2015

Hi friends,

I am new to VHDL , FPGA and Qaurtus. I am getting having a hard time in compiling a VHDL model in Qaurtus ll web edition. The code is below. I compiled it from Modelsim , there it worked well. But, when I tried compiling it from Qaurtus , its is showing some errors that I cannot figure out.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;
ENTITY Decoder4bit is
    port(
        d_in : in std_logic_vector(3 to 0);
        d_out: out std_logic_vector(3 to 0)
        );
END Decoder4bit;
ARCHITECTURE Behaviour of Decoder4bit is BEGIN
  U1:  PROCESS (d_in) BEGIN
        if( d_in = "0000") then d_out <= "1111";
        end if;
        if( d_in = "0001") then d_out <= "1110";
        end if;
        if( d_in = "0010") then d_out <= "1101";
        end if;
        if( d_in = "0011") then d_out <= "1100";
        end if;
        if( d_in = "0100") then d_out <= "1011";
        end if;
        if( d_in = "0101") then d_out <= "1010";
        end if;
        if( d_in = "0110") then d_out <= "1001";
        end if;
        if( d_in = "0111") then d_out <= "1000";
        end if;
        if( d_in = "1000") then d_out <= "0111";
        end if;
        if( d_in = "1001") then d_out <= "0110";
        end if;
        if( d_in = "1010") then d_out <= "0101";
        end if;
        if( d_in = "1011") then d_out <= "0100";
        end if;
        if( d_in = "1100") then d_out <= "0011";
        end if;
        if( d_in = "1101") then d_out <= "0010";
        end if;
        if( d_in = "1110") then d_out <= "0001";
        end if;
        if( d_in = "1111") then d_out <= "0000";
        end if;
     END PROCESS;
END Behaviour;

This is a simple decoder and it doesnot complie. The Quartus ll synthesizer gives erros as below.

Error (12061): Can't synthesize current design -- Top partition does not contain any logic

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 20 warnings

Error: Peak virtual memory: 1146 megabytes

Error: Processing ended: Fri Aug 7 16:47:04 2015

Error: Elapsed time: 00:00:08

Error: Total CPU time (on all processors): 00:00:20

Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 20 warnings

any help will be greatly appreciated. I will have to use the Cyclone V FPGA later for implementing some complex designs. This is just a start. Also, I have 2 more questions.

1.What is the differance between Qaurtus ll and Model SIM ?

2.Can't run test-bences in Quartus II ?

Thanks,

Kannoth

Altera_Forum · ‎08-07-2015

That is an of error, can you post the whole project?

This decoder is nothing more than an inverter though.

In answer to your question. Quartus computed the code to put on the fpga, modulation only stimulates the code.

Altera_Forum · ‎08-07-2015

The synthesis tool noticed that all of the if statements are in parallel, so it chooses the very last one to implement. It should reduce it to a combinatorial latch that clears all of the output bits once it sees all of the input bits set; there is no way for it to set any of the output bits.

In simulation, each if statement in turn is evaluated, and only the one where the input matches does the evaluation result in an assignment. So you have a synthesis/simulation mismatch.

Your decoder is best implemented with a case statement.

As for the specific errors, who can tell? Is your decoder the top level or is there something else you're not showing us?

"1.What is the differance between Qaurtus ll and Model SIM ?"

Quartus II is the FPGA synthesis and implementation tool. It takes your source files and your constraints and (hopefully) fits them into the specified FPGA device.

ModelSim is a simulation tool. You use it to simulation and verify the individual sources and the entire design. You have to write the test benches which stimulate the design and verify its outputs. You will also need to write or obtain functional models of any external devices to which the FPGA connects.

"2.Can't run test-bences in Quartus II ?"

Quartus II can launch a simulation in ModelSim, but it's easier to just run ModelSim standalone with your own test benches.

Altera_Forum · ‎08-08-2015

It seems that there is no top design file selected in your project.

You should start with some VHDL tutorial and looking at some other peoples code.

1. The inferred latches should not intended to be here

2. Don't know why ModelSim does not complain but also your in and output ports are all 0 ranged. You meant "3 downto 0" and not "3 to 0"

3. All what you are doing is a simple "data_out <= not data_in"

Altera_Forum · ‎08-08-2015

Thanks you very much for all your answers and support. I really appreciate it. As I am new to VHDL , I was little confused about the syntax. The error was solved after I made "(3 to 0)" to "(3 downto 0)" (which was I really intended to do) then the synthesis was successful. I think I am getting familiarized with VHDL and FPGA :D . I am doing a project to implement a communication protocol in FPGA. So as to get started with VHDL, I randomly wrote that module decoder, just to understand and familiarize with VHDL. There is no practical importance to it in my project.

Altera_Forum · ‎08-12-2015

--- Quote Start ---

The synthesis tool noticed that all of the if statements are in parallel, so it chooses the very last one to implement. It should reduce it to a combinatorial latch that clears all of the output bits once it sees all of the input bits set; there is no way for it to set any of the output bits

--- Quote End ---

In fact it is inside a process, so each "if" statement will be evaluated by the synthesizer to generate the logic. But I agree that a "case" statement would be more elegant.

In both cases it is advisable to also put a default output (either before all the ifs in the original example, or as an "others" case statement) to avoid generation of latches if we forgot an input value.