VHDL Configuration Specification and Functional Simulation

[emaferna]

Hello to everyone,
I have:
*) an entity (a trivial and 2-input) with 3 architectures
*) a configuration specification (at the end of the entity file itself, in which specific for the entity to use architecture 2.
*) a test bench performed in ModelSim-Altera
I can't make the configuration effective, as the last architecture described is always simulated.
How do I make a configuration other than the default one take effect?
Could some of you give me a small working example, or tell me how to do it properly?
Thanks.

Here the code of the top file:
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------

entity my_and2 is
generic (delay: DELAY_LENGTH: = 5 ns);
port (
x, y: in STD_LOGIC;
z: out STD_LOGIC
);
end entity my_and2;

--------------------------------------------
- architecture with a delay of 5 ns
architecture arch1 of my_and2 is
begin
z <= x and y after delay;
end architecture arch1;

--------------------------------------------
- architecture with delay of 10 ns
architecture arch2 of my_and2 is
begin
z <= x and y after 10 ns;
end architecture arch2;

--------------------------------------------
- architecture without delay
architecture arch3 of my_and2 is
signal xy: STD_LOGIC_VECTOR (0 to 1);
begin
xy <= x & y;
with xy select
z <= '1' when "11",
'0' when others;
end architecture arch3;

----------------------------------------------
-
configuration And2Config of my_and2 is
for arch2
end for;
end configuration And2Config;
-
----------------------------------------------

Here the code of the Test bench file:

----------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY tb IS
END tb;
ARCHITECTURE tb_arch OF tb IS
- constants
- signals
SIGNAL x: STD_LOGIC;
SIGNAL y: STD_LOGIC;
SIGNAL z: STD_LOGIC;
COMPONENT my_and2
PORT (
x: IN STD_LOGIC;
y: IN STD_LOGIC;
z: OUT STD_LOGIC
);
END COMPONENT;
BEGIN
i1: my_and2
PORT MAP (
- list connections between master ports and signals
x => x,
y => y,
z => z
);

- x
t_prcs_x: PROCESS
BEGIN
x <= '0';
WAIT FOR 220000 ps;
x <= '1';
WAIT FOR 200000 ps;
x <= '0';
WAIT;
END PROCESS t_prcs_x;

- y
t_prcs_y: PROCESS
BEGIN
y <= '0';
WAIT FOR 290000 ps;
y <= '1';
WAIT FOR 430000 ps;
y <= '0';
WAIT;
END PROCESS t_prcs_y;
END tb_arch;

----------------------------------------------

[SyafieqS]

Hi Emanuele,

I found a very helpful reference for you related CONFIGURATION CONSTRUCTS EXPLAINED. 

https://vhdlwhiz.com/configuration-constructs-explained/

Regards

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.