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VHDL Traffic Light - How to make signals viewable in simulation?

Altera_Forum
Honored Contributor II
‎06-10-2016 03:43 AM
1,691 Views

Hi there, relatively new to VHDL. 

 

At the end of this description I will post my VHDL code and Test Bench. When I simulate the code, the timing seems to be off, I want it to wait 15 clock cycles to go from Main Green (MG), Side Red (SR) to MY SR, and then 3 clock cycles to go to MR SG, then another 15 to go to MR SY, and so on... 

 

To keep count, I have to declare signals Count, in addition to signals state type to control the states. 

 

How do I show the signals in my simulation? All it shows me is the input and output values but I'd like to see the signal values! Even to see the state values would be chillin'. 

 

Thanks! 

 

 

 

DESIGN CODE: 

 

---------------------------------------------------------------------------------- 

-- Company:  

-- Engineer:  

--  

-- Create Date: 05/24/2016 10:20:40 AM 

-- Design Name:  

-- Module Name: Traffic_Light_VHDL - Behavioral 

-- Project Name:  

-- Target Devices:  

-- Tool Versions:  

-- Description:  

--  

-- Dependencies:  

--  

-- Revision: 

-- Revision 0.01 - File Created 

-- Additional Comments: 

--  

---------------------------------------------------------------------------------- 

 

 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use ieee.std_logic_arith.all; 

-- Uncomment the following library declaration if using 

-- arithmetic functions with Signed or Unsigned values 

use IEEE.NUMERIC_STD.ALL; 

use ieee.std_logic_unsigned.all; 

 

 

-- Uncomment the following library declaration if instantiating 

-- any Xilinx leaf cells in this code. 

--library UNISIM; 

--use UNISIM.VComponents.all; 

 

 

entity Traffic_Light_VHDL is 

Port ( 

Reset : in std_logic; 

clk : in std_logic; 

MG : out STD_LOGIC; 

MY : out STD_LOGIC; 

MR : out STD_LOGIC; 

SG : out STD_LOGIC; 

SY : out STD_LOGIC; 

SR : out STD_LOGIC  

); 

end Traffic_Light_VHDL; 

 

 

architecture Behavioral of Traffic_Light_VHDL is 

 

 

type state_type is (st0, st1, st2, st3); 

signal PS, NS : state_type; 

signal state : state_type; 

signal Count : std_logic_vector(3 downto 0); 

 

 

begin 

process(clk, Reset) 

begin 

if (Reset = '1') then 

state <= st0; 

Count <= "0000"; 

elsif (rising_edge(clk)) then 

state <= NS; 

end if; 

end process;  

 

 

process(clk) 

begin 

case state is 

when st0 =>  

if (Count < "1111") then 

Count <= Count + 1; 

else  

NS <= st1; 

Count <= "0000"; 

end if; 

when st1 => 

if (Count < "0011") then 

Count <= Count + 1; 

else 

NS <= st2; 

Count <= "0000"; 

end if; 

when st2 => 

if (Count < "1111") then 

Count <= Count + 1; 

else 

NS <= st3; 

Count <= "0000"; 

end if; 

when st3 => 

if (Count < "0011") then 

Count <= Count + 1; 

else 

NS <= st0; 

Count <= "0000"; 

end if; 

when others =>  

NS <= st0; 

end case; 

end process; 

 

process(state) 

begin 

case state is 

when st0 => 

MG <= '1'; 

SR <= '1'; 

MY <= '0'; 

SY <= '0'; 

MR <= '0'; 

SG <= '0'; 

when st1 => 

MG <= '0'; 

SR <= '1'; 

MY <= '1'; 

SY <= '0'; 

MR <= '0'; 

SG <= '0'; 

when st2 => 

MG <= '0'; 

SR <= '0'; 

MY <= '0'; 

SY <= '0'; 

MR <= '1'; 

SG <= '1'; 

when st3 => 

MG <= '0'; 

SR <= '0'; 

MY <= '0'; 

SY <= '1'; 

MR <= '1'; 

SG <= '0'; 

when others => 

MG <= '1'; 

SR <= '1'; 

MY <= '0'; 

SY <= '0'; 

MR <= '0'; 

SG <= '0'; 

end case; 

end process; 

 

 

end Behavioral; 

 

 

 

 

---TEST BENCH 

 

 

---------------------------------------------------------------------------------- 

-- Company:  

-- Engineer:  

--  

-- Create Date: 05/25/2016 06:52:32 PM 

-- Design Name:  

-- Module Name: Traffic_Light_Sim - Behavioral 

-- Project Name:  

-- Target Devices:  

-- Tool Versions:  

-- Description:  

--  

-- Dependencies:  

--  

-- Revision: 

-- Revision 0.01 - File Created 

-- Additional Comments: 

--  

---------------------------------------------------------------------------------- 

 

 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use ieee.std_logic_arith.all; 

use ieee.std_logic_unsigned.all; 

-- Uncomment the following library declaration if using 

-- arithmetic functions with Signed or Unsigned values 

use IEEE.NUMERIC_STD.ALL; 

 

 

-- Uncomment the following library declaration if instantiating 

-- any Xilinx leaf cells in this code. 

--library UNISIM; 

--use UNISIM.VComponents.all; 

entity Traffic_Light_Sim is 

 

 

end Traffic_Light_Sim; 

 

 

architecture Behavioral of Traffic_Light_Sim is 

 

 

component Traffic_Light_VHDL is 

Port ( Reset : in std_logic; 

clk : in std_logic; 

MG : out STD_LOGIC; 

MY : out STD_LOGIC; 

MR : out STD_LOGIC; 

SG : out STD_LOGIC; 

SY : out STD_LOGIC; 

SR : out STD_LOGIC); 

end component; 

 

 

signal TReset : std_logic; 

signal Tclk : std_logic; 

signal TMG : std_logic; 

signal TMY : std_logic; 

signal TMR : std_logic; 

signal TSG : std_logic; 

signal TSY : std_logic; 

signal TSR : std_logic; 

 

 

begin 

 

 

uut : Traffic_Light_VHDL port map(TReset, Tclk, TMG, TMY, TMR, TSG, TSY, TSR); 

 

 

process begin 

Tclk <= '0'; 

wait for 1 ns; 

Tclk <= '1'; 

wait for 1 ns; 

end process; 

 

 

process begin 

wait for 20ns; 

TReset <= '1'; 

 

 

wait for 20ns; 

 

 

TReset <= '0'; 

 

 

wait for 200ns; 

 

 

end process; 

 

 

end Behavioral;
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Altera_Forum
Honored Contributor II
‎06-10-2016 04:30 AM
935 Views

Update: Now the timing works just how I want it, with the 15 and 3 clock cycles per change of state, and I made it more efficient. 

 

If someone could still tell me how to bring out internal signal in the simulation that would be appreciated, thank you. 

 

 

 

---------------------------------------------------------------------------------- 

-- Company:  

-- Engineer:  

--  

-- Create Date: 05/24/2016 10:20:40 AM 

-- Design Name:  

-- Module Name: Traffic_Light_VHDL - Behavioral 

-- Project Name:  

-- Target Devices:  

-- Tool Versions:  

-- Description:  

--  

-- Dependencies:  

--  

-- Revision: 

-- Revision 0.01 - File Created 

-- Additional Comments: 

--  

---------------------------------------------------------------------------------- 

 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use ieee.std_logic_arith.all; 

-- Uncomment the following library declaration if using 

-- arithmetic functions with Signed or Unsigned values 

use IEEE.NUMERIC_STD.ALL; 

use ieee.std_logic_unsigned.all; 

 

-- Uncomment the following library declaration if instantiating 

-- any Xilinx leaf cells in this code. 

--library UNISIM; 

--use UNISIM.VComponents.all; 

 

entity Traffic_Light_VHDL is 

Port ( 

Reset : in std_logic; 

clk : in std_logic; 

MG : out STD_LOGIC; 

MY : out STD_LOGIC; 

MR : out STD_LOGIC; 

SG : out STD_LOGIC; 

SY : out STD_LOGIC; 

SR : out STD_LOGIC  

); 

end Traffic_Light_VHDL; 

 

architecture Behavioral of Traffic_Light_VHDL is 

 

type state_type is (st0, st1, st2, st3); 

--signal PS, NS : state_type; 

signal state : state_type; 

signal Count : std_logic_vector(3 downto 0); 

 

begin 

process(clk, Reset) 

begin 

if (Reset = '1') then 

state <= st0; 

Count <= "0000"; 

elsif (rising_edge(clk)) then 

case state is 

when st0 =>  

if (Count < "1111") then 

Count <= Count + 1; 

else  

state <= st1; 

Count <= "0000"; 

end if; 

when st1 => 

if (Count < "0011") then 

Count <= Count + 1; 

else 

state <= st2; 

Count <= "0000"; 

end if; 

when st2 => 

if (Count < "1111") then 

Count <= Count + 1; 

else 

state <= st3; 

Count <= "0000"; 

end if; 

when st3 => 

if (Count < "0011") then 

Count <= Count + 1; 

else 

state <= st0; 

Count <= "0000"; 

end if; 

when others =>  

state <= st0; 

end case; 

end if; 

end process; 

 

process(state) 

begin 

case state is 

when st0 => 

MG <= '1'; 

SR <= '1'; 

MY <= '0'; 

SY <= '0'; 

MR <= '0'; 

SG <= '0'; 

when st1 => 

MG <= '0'; 

SR <= '1'; 

MY <= '1'; 

SY <= '0'; 

MR <= '0'; 

SG <= '0'; 

when st2 => 

MG <= '0'; 

SR <= '0'; 

MY <= '0'; 

SY <= '0'; 

MR <= '1'; 

SG <= '1'; 

when st3 => 

MG <= '0'; 

SR <= '0'; 

MY <= '0'; 

SY <= '1'; 

MR <= '1'; 

SG <= '0'; 

when others => 

MG <= '1'; 

SR <= '1'; 

MY <= '0'; 

SY <= '0'; 

MR <= '0'; 

SG <= '0'; 

end case; 

end process; 

 

 

end Behavioral;
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Altera_Forum
Honored Contributor II
‎06-10-2016 04:59 AM
935 Views

you click on the sim tab, then the entity where you want to get the signal from. Then you drag the correcsponding signals you want from the objects window onto the wave window.

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Altera_Forum
Honored Contributor II
‎06-15-2016 05:12 AM
935 Views

use the following command in transcript window 

 

add wave Traffic_Light_Sim/uut/* 

 

* indicates that all the signals from the uut will be displayed. Also you can add individual signals by replacing * with the signal name
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