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Altera_Forum
Honored Contributor I
814 Views

VHDL code error

https://alteraforum.com/forum/attachment.php?attachmentid=15816&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15818&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15819&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15820&stc=1 Hello,  

 

I am trying to do Bit Error Rate Testor on my FPGA Altera Cyclone V board and SFP-HSMC. I am trying to send 3Gbps of data where as the maximum the transceiver or receiver can send or receive is 3.25Gbps. I am getting few errors which I am not able to figure out where the error exactly is. I request you to please let me know what changes do I need to make in the code. 

 

Thanks a ton in advance.
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3 Replies
Altera_Forum
Honored Contributor I
28 Views

Hello, I am attaching rest of the code here. Sorry about that. 

 

Test Bench code: 

 

LIBRARY ieee; 

USE ieee.std_logic_1164.ALL; 

 

-- Uncomment the following library declaration if using 

-- arithmetic functions with Signed or Unsigned values 

--USE ieee.numeric_std.ALL; 

 

ENTITY bertb IS 

END bertb; 

 

ARCHITECTURE behavior OF bertb IS 

 

-- Component Declaration for the Unit Under Test (UUT) 

 

COMPONENT BERCalculator 

PORT( 

------------ Clock ---------------------- 

CLK_IN : in std_logic;  

Key : in std_logic_vector (3 downto 0); 

------------ SEG7 ----------------------- 

HEX0 : out std_logic_vector (7 downto 0); 

HEX1 : out std_logic_vector (7 downto 0); 

HEX2 : out std_logic_vector (7 downto 0); 

HEX3 : out std_logic_vector (7 downto 0); 

----------- Received_Signals ------------- 

RX_Received : in std_logic_vector (255 downto 0); 

TX_Transmitted : in std_logic_vector (175 downto 0) 

); 

END COMPONENT; 

 

--Inputs 

signal CLK_IN : std_logic := '0'; 

signal key : in std_logic_vector (3 downto 0) := (others => '1'); 

signal RX_Received : in std_logic_vector (255 downto 0); 

signal TX_Transmitted :in std_logic_vector (175 downto 0) 

 

--Outputs 

signal HEX0 : =out std_logic_vector (7 downto 0); 

signal HEX1 : out <=std_logic_vector (7 downto 0); 

signal HEX2 : out <=std_logic_vector (7 downto 0); 

signal HEX3 : out <=std_logic_vector (7 downto 0); 

 

-- Clock period definitions 

constant clock_period : time := 20 ns; 

 

BEGIN 

 

-- Instantiate the Unit Under Test (UUT) 

uut: up_down_counter PORT MAP ( 

CLK_IN => CLK_IN, 

key => key, 

RX_Received => RX_Received, 

HEX0=> HEX0, 

HEX1=> HEX1, 

HEX2=> HEX2, 

HEX3=> HEX3, 

TX_Transmitted => TX_Transmitted 

); 

 

-- Clock process definitions 

clock_process :process 

begin 

CLK_IN <= '0'; 

wait for clock_period/2; 

CLK_IN <= '1'; 

wait for clock_period/2; 

end process; 

 

-- Stimulus process 

stim_proc: process 

begin 

-- hold reset state for 100 ns. 

RX_Received: in std_logic_vector (255 downto 0):= (others => '0'); 

wait for 200 ns; 

RX_Received: in std_logic_vector (255 downto 0):= (others => '1'); 

wait for 100 ns; 

TX_Received: in std_logic_vector (175 downto 0):= (others => '1'); 

wait for 100 ns; 

TX_Received: in std_logic_vector (175 downto 0):= (others => '0'); 

end process; 

 

END;
Altera_Forum
Honored Contributor I
28 Views

Hi, 

--- Quote Start ---  

--Inputs 

signal CLK_IN : std_logic := '0'; 

signal key : in std_logic_vector (3 downto 0) := (others => '1'); 

signal RX_Received : in std_logic_vector (255 downto 0); 

signal TX_Transmitted :in std_logic_vector (175 downto 0) 

 

--Outputs 

signal HEX0 : =out std_logic_vector (7 downto 0); 

signal HEX1 : out <=std_logic_vector (7 downto 0); 

signal HEX2 : out <=std_logic_vector (7 downto 0); 

signal HEX3 : out <=std_logic_vector (7 downto 0);  

--- Quote End ---  

 

signal doesn`t required direction. 

 

--- Quote Start ---  

clock_process rocess  

--- Quote End ---  

 

clock_process : process 

 

 

--- Quote Start ---  

stim_proc: process 

begin 

-- hold reset state for 100 ns. 

RX_Received: in std_logic_vector (255 downto 0):= (others => '0'); 

wait for 200 ns; 

RX_Received: in std_logic_vector (255 downto 0):= (others => '1'); 

wait for 100 ns; 

TX_Received: in std_logic_vector (175 downto 0):= (others => '1'); 

wait for 100 ns; 

TX_Received: in std_logic_vector (175 downto 0):= (others => '0'); 

end process;  

--- Quote End ---  

 

Modify like below, 

RX_Received <= (others => '0'); 

 

I would suggest go through the online training & check the attached modified code, 

https://www.altera.com/support/training/course/ohdl1110.html 

LIBRARY ieee;USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY bertb IS END bertb; ARCHITECTURE behavior OF bertb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT BERCalculator PORT( ------------ Clock ---------------------- CLK_IN : in std_logic; Key : in std_logic_vector (3 downto 0); ------------ SEG7 ----------------------- HEX0 : out std_logic_vector (7 downto 0); HEX1 : out std_logic_vector (7 downto 0); HEX2 : out std_logic_vector (7 downto 0); HEX3 : out std_logic_vector (7 downto 0); ----------- Received_Signals ------------- RX_Received : in std_logic_vector (255 downto 0); TX_Transmitted : in std_logic_vector (175 downto 0) ); END COMPONENT; --Inputs signal CLK_IN : std_logic := '0'; signal key : std_logic_vector (3 downto 0) := (others => '1'); signal RX_Received : std_logic_vector (255 downto 0); signal TX_Transmitted : std_logic_vector (175 downto 0); --Outputs signal HEX0 : std_logic_vector (7 downto 0); signal HEX1 : std_logic_vector (7 downto 0); signal HEX2 : std_logic_vector (7 downto 0); signal HEX3 : std_logic_vector (7 downto 0); -- Clock period definitions constant clock_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: up_down_counter PORT MAP ( CLK_IN => CLK_IN, key => key, RX_Received => RX_Received, HEX0=> HEX0, HEX1=> HEX1, HEX2=> HEX2, HEX3=> HEX3, TX_Transmitted => TX_Transmitted ); -- Clock process definitions clock_process : process begin CLK_IN <= '0'; wait for clock_period/2; CLK_IN <= '1'; wait for clock_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. RX_Received <= (others => '0'); wait for 200 ns; RX_Received <= (others => '1'); wait for 100 ns; TX_Transmitted <= (others => '1'); wait for 100 ns; TX_Transmitted <= (others => '0'); end process; END; 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards 

Vikas Jathar  

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
28 Views

Hi, 

Have you resolved the issue? 

 

Best Regards 

Vikas Jathar  

(This message was posted on behalf of Intel Corporation)
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