Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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resetn for all HDL module ?

Honored Contributor II


I have HDL module (is a counter) implemented with OpenCL kernel (like example 1 in Intel examples). This HDL module is called many times in the same kernel. As I understand each call of HDL module will instantiate one module in FPGA. So, for example, if I call the same HDL module 4 times in the same kernel. The 4 HDL module (the 4 counter) are SYNCHRONIZED with the same RESET and they will start at the same time or not ? 

Thank you,
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