VHDL code for 16 to 1 mux using Nand gates

[Altera_Forum]

can neone just tell me how i can implemnet it using structural.. 

because i have 16 gates involved inthis.. and only structural modelling will make it easier.. but i have to declare a component of 5 input nand gate that is one input and 4 select line.. also i have to take not of select lines in some places. but i don't knw how to do that.. is this valid n1:nand2 portmap(i(0),(not S1),(not S2),(not S3),(not S4),Z(1)) I IS INPUT, Z is signal vector defined for output of each nand gate.. please help.:mad: :mad: :mad:

[Altera_Forum]

please reply fast i have my exam today..

[Altera_Forum]

Try this idea: 

 if you want to select in0 when select = 0000 then it means:   select-------in0-------out 0000---------0-------0 0000---------1-------1   hence for nand gate invert all select lines and output and you get:   select--------in0--------nand out inverted 1111----------0---------0 1111----------1---------1   for in1 when select = 0001 invert the first 3 lines and so on

[Altera_Forum]

ya i know that.. 

but i have asked it how to do with structural.. i ahve written in my question that i have to inver the input of select lines but how in structural..?

[Altera_Forum]

ok, then all you need just connect nodes.  

Quartus wouldn't let gating on ports so you can't use not there. Instead negate the node then connect e.g.:   sel1n <= not sel1;   then connect sel1n to the port

[Altera_Forum]

how to implement this in structural..

[Altera_Forum]

use not gate and connect 

 sel needs 4 not gates then connect output of not gates to input of nand.   please tell your examiner that whether it is structural not/nand or inferred it ends up with same result. if you infer then quartus will do the connection for you. In fact it is not connections of gates but of lookup tables. There are no gates in fpga fabricated as we know them...

[Altera_Forum]

but in structural architecture we can just decalre component, instantiate it, efine signal. but everything is done using component we can't define any value.assign any value .. 

or can we.. if yes then how.. please elaborate..

[Altera_Forum]

sorry what values. can you explain your design a bit more.

[Altera_Forum]

kaz, you're right about different implementation methods for the same logic finally ending up in the same gate level netlist. But in VHDL text books, it's usual to distinguish these methods systematically and to require the students to solve a given problem by using one method purely. 

 That's possible for the said multiplexer problem, of course. Strictly spoken, the presented solution is not pure structural, because it involves a not operator. You may want to use inverter components for a pure structural solution. But the selection bits are connected correctly so far.  For the 5 input NAND component a name NAND5 rather than NAND2 should be expected. Personally, I would prefer AND5, because positive logic seems more intuitive in my opinion.  In any case, you have to combine the outputs of the 16 AND/NAND gates to form the complete multiplexer.  I see, that the popular VHDL text book enoch o. hwang, digital logic and microprocessor design with vhdl uses also a "structural" NOT gate for it's 2-to-1 multiplexer.

[Altera_Forum]

got it.. 

thnks a lot..