Re: VHDL equivalence

Altera_Forum · ‎03-06-2009

Hi,

I wonder what is the equivalence of this Verilog statement?

assign data = (cs && oe && ! we) ? data_out : 8'bz;

Altera_Forum · ‎03-06-2009

I'm guessing

data <= data_out when cs = '1' and oe = '1' and we = '0' else (others => 'Z');

I don't personally speak Verilog but I'm guessing that the gist is: when the boolean expression "cs and oe and not we" is 1, assign data_out to data otherwise tri-state data. I hope that's nough to make sense of the VHDL above anyway.

Altera_Forum · ‎03-06-2009

THanks Batflink! It should be it.

Altera_Forum · ‎03-06-2009

Sorry I should have said that the above only applies if you are trying to construct a stand-alone concurrent statement. If this is a line in a process then you need to use an "if" clause, i.e:

process (clk)
begin
    if rising_edge (clk) then
        if (cs = '1' and oe = '1' and we = '0' ) then
            data <= data_out;
        else
            data <= (others => 'Z');
        end if;
    end if;
end process;

Altera_Forum · ‎03-06-2009

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I should have said that the above only applies if you are trying to construct a stand-alone concurrent statement

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That's the same with Verilog assign. It doesn't work in an always block.