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Altera_Forum
Honored Contributor I
764 Views

VHDL help with code

Hi! 

Can anyone help me ih writing VHDL code for this diagra? I need simulation results too. Thanks ! :))
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6 Replies
Altera_Forum
Honored Contributor I
50 Views

And what help do you need? What have you have so far and what problems do you have?

Altera_Forum
Honored Contributor I
50 Views

 

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And what help do you need? What have you have so far and what problems do you have? 

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I need code in vhdl, I mean: library ieee etc. Look at scheme. I need this to school and I don't know how to write this. Please help :D
Altera_Forum
Honored Contributor I
50 Views

 

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Could you explain me how it works? I'm trying to write code in vhdl which will be works like this scheme, but I don't understand how to do it.
Altera_Forum
Honored Contributor I
50 Views

There are plenty of VHDL tutorials and text books out there. We will not do your work for you. You need to do it yourself and we are here to help if you get stuck.

Altera_Forum
Honored Contributor I
50 Views

okey so tell me what is A1 A2 etc. Input or Output ? I have some code but i don't understand it... I really need this... Please help me ;c 

 

 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

 

entity projekt is 

port(Up,Down, : in std_logic; 

A0, A1, A2, A3: out std_logic); 

end projekt; 

 

architecture przerzutnik of projekt is 

 

component T_FF is 

port (T: in std_logic 

Clock: in std_logic 

Out: out std_logic); 

signal tmp: std_logic; 

begin 

process (Clock) 

begin 

if Clock'event and Clock='1' then 

 

if T='0' then 

tmp <= tmp; 

elsif T='1' then 

tmp <= not (tmp); 

end if; 

end if; 

end process; 

Out <= tmp; 

end przerzutnik; 

 

begin 

T_FF: T1 port map(T 

T_FF: T2 port map 

T_FF: T3 port map 

T_FF: T4 port map
Altera_Forum
Honored Contributor I
50 Views

A0-3 are all outputs, because they have out written next to them.  

I highly suggest reading a VHDL tutorial.
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