VHDL latches

[Altera_Forum]

Hello,  

  I have a warnings in Quartus:  Warning (10631): VHDL Process Statement warning at dma.vhd(449): inferring latch(es) for signal or variable "din_exp", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at salsa_dma.vhd(449): inferring latch(es) for signal or variable "const_exp", which holds its previous value in one or more paths through the process   Suspicious code is looks like this:   SIGNAL din_exp, const_exp : STD_LOGIC_VECTOR(511 DOWNTO 0) ; ... PROCESS(state, const, dout, ram_dout, data_in, din_exp, const_exp, din) VARIABLE din_exp_var, const_exp_var : STD_LOGIC_VECTOR(511 DOWNTO 0) ; BEGIN CASE state IS WHEN idle_state => din_exp_var := data_in(511 DOWNTO 0) XOR data_in(1023 DOWNTO 512) ; const_exp_var := data_in(511 DOWNTO 0) XOR data_in(1023 DOWNTO 512) ; WHEN s0_1 => din_exp_var := const XOR dout ; const_exp_var := const XOR dout ; WHEN s1 => din_exp_var := din_exp ; const_exp_var := const_exp ; -- other states WHEN OTHERS => din_exp_var := const XOR dout ; const_exp_var := const XOR dout ; END CASE ; din_exp <= din_exp_var ; const_exp <= const_exp_var ; END PROCESS ;   In state s1 I don't want to change anything to my signal assignment, also previous values must be saved. There are no default values for these signals. Is there a latch needed? Is this code ok? Or should I change anything? How?  Thank you!

[Altera_Forum]

When want a signal hold its value until some condition occurs, you should use register instead of latches. Registers needs a clock signal. You may modify your code this way: 

 process(clk,clr) begin  if(clr='1') then  din_reg <= din_next;  elsif(clk'event and clk='1')then  end if; end process;   PROCESS(...)  din_next <= din_reg;  BEGIN  CASE state IS  WHEN idle_state =>     din_next <= data_in(511 DOWNTO 0) XOR data_in(1023 DOWNTO 512) ;    WHEN s0_1 =>   din_next <= const XOR dout ;    WHEN s1 =>   din_next <= din_exp ;    WHEN OTHERS =>  din_next <= const XOR dout ;    END CASE ;  END PROCESS ;  The same for the rest of signals.

[Altera_Forum]

I think you've messed up your code a little bertulus. din_reg <= din_next should be assigned inside the clock. also, din_next <= din_reg should be inside the begin. 

  Or make life even easier for yourself and others - use a single process clocked state machine (not 2).

[Altera_Forum]

oh yes, i place this assigment in the wrong line. Sorry linas. 

 Tricky, about writing sequential circuits in 1 or 2 blocks, theorically there are no difference in the description. But , it makes difference writting in 1 or 2 blocks in the Quartus tool? For example, a counter written in 1 block, infers a better circuit ( fewer LEs or a faster implementation) ?

[Altera_Forum]

As I understand it, the two process style comes from the days when people (and tools) required separate processes for sequential logic and registers. And its a style thats never gone away. For beginners (and others) it is prone to latches.  

Using a single clocked process removes these problems, and tools have no problems understanding them. I have no doubts you will get the same results with both (or if anything, you will get minor usage differences).  For me, a single process is more readible (and its all about readbility - not minor quibbles over 1 or 2 luts).

[Altera_Forum]

I, often, use the 2 block style for state machines when I wish to write conditions like 

"if state_current = SOME_STATE and state_next = SOME_OTHER_STATE then ....".  Other than that, I also prefer the 1 block style.  And implementation wise, it's the same.

[Altera_Forum]

Thank you all for help and useful tips. I didn't modify this part much, just removed states with latches. I implemented registers in component one level down in the hierarchy, now everything looks ok.