VHDL probably so simple you could do it in your sleep...but I can't

[Altera_Forum]

I need to write a code that  

 "has two unsigned 6b inputs, inputa and inputb, and two outputs, multresult and iseven.  multresult should give the result, without overflow, when the two inputs are multiplied.  iseven should tell whether the multiplication produced an odd (0) or even (1) value. "   where do I even start? I have absolutely ZERO coding or VHDL experience...

[Altera_Forum]

No we don't code in sleep but we get algorithms only. I won't do that for your homework but just give you some tips: 

declare two 6n inputs as unsigned. declare outut as 12b then say: output <= in1*in2;  even <= not output(0); -- if 0 it is even finally: done <= '1';

[Altera_Forum]

library IEEE; 

use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all;  entity UNSIGNED_MULTIPLIER6x6 is port ( inputA, inputB : in STD_LOGIC_VECTOR(5 downto 0); multResult: out STD_LOGIC_VECTOR(11 downto 0)); isEven: out STD_LOGIC_VECTOR(1 downto 0); end UNSIGNED_MULTIPLIER6x6;  architecture DATA_FLOW of UNSIGNED_MULTIPLIER6x6 is   multResult <= inputA*inputB; if multResult0=1, then isEven<='0'  else isEven<= '1';   end if; end process; end DATA_FLOW ;

[Altera_Forum]

That's overkill (not sure it even works). Kaz already gave you the answer on a silver platter. VHDL and verilog you can multiply two signals together to get an output. The multiplier result width is the sum of the two input widths. For example if you multiply an 8-bit number by a 4-bit number you should ensure the wire/register that holds the result is 8+4 = 12 bits wide. Kaz also told you how to detect if a result is odd or even... if you don't believe him write some numbers in base 2 and look at the least significant bit.

[Altera_Forum]

Just googled K.I.S.S and was impressed because I was looking for that concept all my life, thanks for the tip. I really feel feverish when I see any spaghetti logic and 

long strings of code. I know it will go wrong. So keep it simple and use others well proven work called various names: functions, ip, cores, +, -, * ...etc. We all build blocks from other blocks and it is waste of time to rebuild what is right on your desk.

[Altera_Forum]

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity UNSIGNED_MULTIPLIER6x6 is port ( inputA, inputB : in unsigned(5 downto 0); multResult: out unsigned(11 downto 0); isEven: out STD_LOGIC ); end entity; architecture rtl of UNSIGNED_MULTIPLIER6x6 is signal Result: unsigned(11 downto 0); begin Result <= inputA*inputB; multResult <= Result; isEven <= not Result(0); end RTL ;

[Altera_Forum]

excelent - you gave him some errors to find himself.

[Altera_Forum]

Thanks Tricky, about the only error I realised so far is that I called the architecture rtl yet there isn't a single register.

[Altera_Forum]

and the fact you forgot the numeric_std library.

[Altera_Forum]

--- Quote Start ---  and the fact you forgot the numeric_std library.  --- Quote End ---    Indeed I tried to put it but wasn't sure of syntax: [std_numeric Vs numeric_std] so I gave up to synopsis library.