VHDL sequential vs concurrent statement

Altera_Forum · ‎01-25-2016

Hi,

I am bit confused over sequential vs concurrent statements in VHDL. In almost all books, it is mentioned as process body will contain sequential statements. Consider following code fragments.


architecture concurrent  of xyz is
signal sig1, sig2 : std_logic;
begin
   out  <=  sig1 or sig2;
   sig1 <= in1 and in2;
   sig2 <= in1 or in2;
end architecture concurrent;


architecture sequential of xyz is
signal sig1, sig2 : std_logic;
begin
process(all)
begin
   out  <=  sig1 or sig2;
   sig1 <= in1 and in2;
   sig2 <= in1 or in2;
end process;
end architecture sequential;

Both fragments results in same RTL view. Whats the difference?

Thank you,

sawaak

Altera_Forum · ‎01-25-2016

This is where you need to understand vhdl mechanics. Firstly, a single line vhdl statement actually infers a process with all the signals on the rhs in the sensitivity list. Si you actually have 3 processes in parallel. Secondly, signals are only updated when a process suspends. When a signal assignment is made, it is only scheduled to be updated at the end of the current delta cycle, so all three signals are updated at the same time.

Altera_Forum · ‎01-25-2016

So to actually answer your question, there's no difference between the two codes

Altera_Forum · ‎01-26-2016

to @sawaak:

You have to learn about dataflow/behaviour/structur concept . Also learn difference between VHDL code for synthesis and for simulation.

by the way this link might be helpful for you http://esd.cs.ucr.edu/labs/tutorial/vhdl_page.html (http://esd.cs.ucr.edu/labs/tutorial/vhdl_page.html)

i think it is old one but feel free to surf the web.

P.S. @Tricky: the result will be the same but will be time for simulation equal too?

and one exception: process(all) requires VHDL-2008 support. it seems so. if i wrong let me know

Altera_Forum · ‎01-26-2016

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P.S. @Tricky: the result will be the same but will be time for simulation equal too?

and one exception: process(all) requires VHDL-2008 support. it seems so. if i wrong let me know

--- Quote End ---

Yes, that is a VHDL 2008 construct, but Quartus and all simulators I know support it.

As for simulation time? are you refering to simulation time or simulator speed?

Sim time is identical for both, as all signals are scheduled to update at the end of any delta where their inputs change. so when in1 or in2 change, out will change 2 deltas later.

As for simulator speed - I would assume they would have decent compiler optimisation to catch these kind of mergable bits of code. You'd have to test you simulator to find out.

Altera_Forum · ‎01-26-2016

Thank you both Tricky and alex96 for your valuable comments. I am trying to figure out the differences.

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Firstly, a single line vhdl statement actually infers a process with all the signals on the rhs in the sensitivity list. Si you actually have 3 processes in parallel.

--- Quote End ---

Yes, this is what happens when we use concurrent statements.

--- Quote Start ---

Secondly, signals are only updated when a process suspends. When a signal assignment is made, it is only scheduled to be updated at the end of the current delta cycle, so all three signals are updated at the same time.

--- Quote End ---

So can I conclude there is no such thing as sequential signal assignment in VHDL?

In most books and online tutorials, e.g. in RTL Hardware Design by Prof Chu, it is written "The syntax of a sequential signal assignment is identical to that of the simple concurrent signal assignment of Chapter 4 except that the former is inside a process"- Page 100. In book, he discussed about assignment to same signal multiple times in a process which results in only last assignment take effect. I can understand that. But what is missing in that book and in all of the online tutorials I have seen so far is example/discussion of sequential signal assignment to multiple signals. It seems there is no difference between sequential signal assignment and concurrent signal assignment in that case, but then why we have sequential signal assignment in the first place and if it is (I mean sequential assignment) executed same as concurrent assignment then why name it different?

@alex96...thank you for the link..

Altera_Forum · ‎01-26-2016

What could blow novice's brain up it is very weak description for differences between dataflow and behaviour paradigms.

----

But if it allowed to say "each concurrent assignment involve indirectly process operator with sensitivy list where all signals that used on right of assignment expression" ?

----

And then if we have fully synchronous design we can put all action in one very big process(clock-signal) (sounds like joke)

And for novice it is worth to ask such questions : "How to describe synchronus design using dataflow paradigm? is it possible?", "Has dataflow paradigm any limitation?"

Altera_Forum · ‎01-26-2016

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So can I conclude there is no such thing as sequential signal assignment in VHDL?

In most books and online tutorials, e.g. in RTL Hardware Design by Prof Chu, it is written "The syntax of a sequential signal assignment is identical to that of the simple concurrent signal assignment of Chapter 4 except that the former is inside a process"- Page 100. In book, he discussed about assignment to same signal multiple times in a process which results in only last assignment take effect. I can understand that. But what is missing in that book and in all of the online tutorials I have seen so far is example/discussion of sequential signal assignment to multiple signals. It seems there is no difference between sequential signal assignment and concurrent signal assignment in that case, but then why we have sequential signal assignment in the first place and if it is (I mean sequential assignment) executed same as concurrent assignment then why name it different?

--- Quote End ---

I think you need to understand - all VHDL is sequential code. All code inside a process is sequential - this is how variables work. But multiple assignments to the same signal sequentially in the same delta will cause the signal assignment to get overridden. I think where you might be getting confused is the fact that all code you've posted is for synthesis. Now lets take a behavioural (non synthesisable example).


process
begin
  ip <= '1';
  op <= ip;
  wait for 0 ns;  -- wait for a single delta
  ip <= '0';
  op < =ip;
  wait;
end process;

Now, if you did not do the second signal assignment, op would be stuck at 'U'.

because of the way signals work, and all communication between processes is done with signals - you can guarantee the order in which things will occur. But you can do things in VHDL where cannot guarantee what order they work - it will come down to how the code was compiled that you have little to no control over:


shared variable sv : std_logic := '1';  --'93 shared variable
process(clk)
begin
  if rising_edge(clk);
    sv := not sv;
  end if;
end process;
process(clk)
begin
  if rising_edge(clk) then
    op <= sv;
  end if;
end process;

Now, you do not know whether op will take the current inverted value, or the value pre inversion in the current delta. It will depend how the compiler compiled the code.

Altera_Forum · ‎02-14-2016

Thank you, Tricky..very much appreciated. Sorry to restart after so long, was badly stuck somewhere else..

So can I conclude that if we do multiple assignments to different signal (within a single process block) then the difference between sequential signal assignment and concurrent signal assignment matter for simulation purposes only. There is no difference for synthesizeable code (e.g. the code I posted in first post)?

Altera_Forum · ‎02-14-2016

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Thank you, Tricky..very much appreciated. Sorry to restart after so long, was badly stuck somewhere else..

So can I conclude that if we do multiple assignments to different signal (within a single process block) then the difference between sequential signal assignment and concurrent signal assignment matter for simulation purposes only. There is no difference for synthesizeable code (e.g. the code I posted in first post)?

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The code you posted was very trivial. But you shouldnt care about the signal assignments in simulation or synthesis. If you get a missmatch between simulation and synthesised hardware, there is a problem - usually a problem of poorly written code.

Ie. never use shared variables!

Altera_Forum · ‎02-15-2016

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The code you posted was very trivial. But you shouldnt care about the signal assignments in simulation or synthesis. If you get a missmatch between simulation and synthesised hardware, there is a problem - usually a problem of poorly written code.

Ie. never use shared variables!

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Thank you..