Verilog HDL CODE Help!

[Altera_Forum]

Cancelled:cry::cry::cry::cool:

[Altera_Forum]

These are basic exercises. 

Looks like an homework? :-)  Spend at least ten minutes looking into an HDL book and we'll see

[Altera_Forum]

Cancelled:cry::cry::cry::cool:

[Altera_Forum]

Cancelled:cry::cry::cry::cool:

[Altera_Forum]

The UD counter looks ok. 

 The MUX uses a command I don't know.   --- Quote Start ---  assign mux_out = (sel)?SOURCE0_IH:SOURCE1_IH:SOURCE2_IH:SOURCE3_IH: SOURCE4_IH:SOURCE5_IH:SOURCE6_IH:SOURCE7_IH;   --- Quote End ---  I only use the conditional operator (?) as a ternary operator. Don't know if can be used in this sense.  I would use a case statement:   --- Quote Start ---  reg mux_out; always @(sel,SOURCE0_IH,SOURCE1_IH, etc.)  case (sel) 3'b000: mux_out = SOURCE0_IH; 3'b001: mux_out = SOURCE1_IH; ... default: mux_out = 1'b0; endcase   --- Quote End ---  

[Altera_Forum]

Cancelled:cry::cry::cry::cool:

[Altera_Forum]

You have to define sel as a bit vector. Now it's a single bit. 

sel; Then the mux code should work.  It has been a nice idea to extend the conditional operator to multiple alternatives in your previous example. Unfortunately the Verilog standard doesn't know it.

[Altera_Forum]

Cancelled:cry::cry::cry::cool:

[Altera_Forum]

sel is an input, not of the reg type.

[Altera_Forum]

Cancelled:cry::cry::cry::cool:

[Altera_Forum]

A simple bit signal can only display values 0 and 1.

[Altera_Forum]

Cancelled:cry::cry::cry::cool: