Verilog HDL Modeul instantiation error

[Junyong]

Hello all,

I'm trying to compile "Stratix 10-Tx PAM4 2x51 Gbps with SMA Design Example 18.1" with my Strati10 Tx Signal Integrity Dev Kit. 

I got an error message below during compilation:

Error(13452): Verilog HDL Module Instantiation error at native0_altera_xcvr_native_s10_etile_181_32cenqy.sv(3058): module "ct3_xcvr_native" has no parameter named "hssi_aibnd_rx_aib_ber_margining_ctrl"

Could you please let me know how to handle with the issue?

[FvM · Accepted solution]

Hi,
guess you are using a newer version than Quartus 18.1? The example design built with 18.1 will probably need IP regeneration or even some modifications to work with newer Quartus versions. Problems of this kind have been frequently reported.

[Junyong]

Thank you for your reply, FvM.

The version of Intel Quartus Prime Pro installed on my PC is 18.0.

It would be due to the version as you said. I'll try with Quartus 18.1.

Best Regards,

Junyong

[SyafieqS]

For example design, you are encouraged to use same version as mentioned to avoid expected issue e.g. IP upgrades and compatibility.

Use different version is at your own responsibility.

May revert to 18.1 per mentioned.

[Junyong]

Yes. After matching Quartus version to the example file, it was effective.

I faced another issue, but the issue I addressed was resolved.

Thank you very much for your help. 

Best Regards,

Junyong

[SyafieqS]

Let me know if there is any update

[Junyong]

It was resolved. Thanks.

[SyafieqS]

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