Verilog HDL question

[Altera_Forum]

I've seen HDL code that merges the input (or output) and the wire (or reg) declaration in a single instruction. 

 That is instead of :  module dummy(A,B) input A; output [3:0] B; wire A; reg [3:0] B; ... endmodule  some code uses the following, that is more compact and seems also to be less error prone:  module dummy(A,B) input wire A; output reg [3:0] B;  ... endmodule  My questions are: 1) Is this syntactically correct? 2) Is this only available in Verilog 2001 standard? 3) Do you suggest this coding style? Are there drawbacks (compatibility issues, portability issues, readability issues)?  Thx

[Altera_Forum]

for an input like A you do not need to use wire, in fact i haven't seen that yet so it could be possible or even not allowed 

wires can only be used for outputs (as far as i know)  you could also write module dummy ( input A, output reg [3:0] B );  i personaly does not declared like my example as this could lead into problems when using wires and assigns. so i prefer this one  module dummy ( A,B,C ); input A; output reg [3:0] B; output [3:0] C;  wire [3:0] C; assign C=B; endmodule

[Altera_Forum]

*edit* Just realized I said the same thing as MSchmitt :)

[Altera_Forum]

Actually, it's OK to declare an input as "wire". 

In fact, the reason you don't need to do it is because, by default, Verilog assumes everything is a wire. Even undeclared variables...  Some of us like to begin their Verilog modules with "`default_nettype none" to make sure the compiler yields an error for undeclared stuff. In such case, you need to explicitly declare the inputs as wires.  In general, my Verilog looks something like:  `default_nettype none module foo ( input wire [1:0] a, output reg [1:0] b, output wire [1:0] c );  ... endmodule